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Commit 60ad8467 authored by Stefan Agner's avatar Stefan Agner Committed by Shawn Guo
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ARM: imx: pllv3: add shift for frequency multiplier 



Add shift capabilties for the frequency multiplier (DIV_SELECT) to
support Vybrid's USB PLL oddity. The PLL3 and PLL7 are the only
PLL control registers which have the DIV_SELECT bit shifted by
one. Be aware, there are known documentation errors in the
reference manual too.

Signed-off-by: default avatarStefan Agner <stefan@agner.ch>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent da06aae8

arch/arm/mach-imx/clk-pllv3.c

+7 −3
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 
 * @base:	 base address of PLL registers

 * @powerup_set: set POWER bit to power up the PLL

 * @div_mask:	 mask of divider bits

 * @div_shift:	 shift of divider bits

 *

 * IMX PLL clock version 3, found on i.MX6 series.  Divider for pllv3

 * is actually a multiplier, and always sits at bit 0.
@@ -40,6 +41,7 @@ struct clk_pllv3 { 
	void __iomem	*base;

	bool		powerup_set;

	u32		div_mask;

	u32		div_shift;

};



#define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
@@ -97,7 +99,7 @@ static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw, 
					   unsigned long parent_rate)

{

	struct clk_pllv3 *pll = to_clk_pllv3(hw);

	u32 div = readl_relaxed(pll->base)  & pll->div_mask;

	u32 div = (readl_relaxed(pll->base) >> pll->div_shift)  & pll->div_mask;



	return (div == 1) ? parent_rate * 22 : parent_rate * 20;

}
@@ -125,8 +127,8 @@ static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate, 
		return -EINVAL;



	val = readl_relaxed(pll->base);

	val &= ~pll->div_mask;

	val |= div;

	val &= ~(pll->div_mask << pll->div_shift);

	val |= (div << pll->div_shift);

	writel_relaxed(val, pll->base);



	return clk_pllv3_wait_lock(pll);
@@ -295,6 +297,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 
	case IMX_PLLV3_SYS:

		ops = &clk_pllv3_sys_ops;

		break;

	case IMX_PLLV3_USB_VF610:

		pll->div_shift = 1;

	case IMX_PLLV3_USB:

		ops = &clk_pllv3_ops;

		pll->powerup_set = true;

arch/arm/mach-imx/clk-vf610.c

+2 −2
Original line number Diff line number Diff line
@@ -172,11 +172,11 @@ static void __init vf610_clocks_init(struct device_node *ccm_node) 


	clk[VF610_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll1", "pll1_bypass_src", PLL1_CTRL, 0x1);

	clk[VF610_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", PLL2_CTRL, 0x1);

	clk[VF610_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB,     "pll3", "pll3_bypass_src", PLL3_CTRL, 0x1);

	clk[VF610_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB_VF610,     "pll3", "pll3_bypass_src", PLL3_CTRL, 0x2);

	clk[VF610_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV,      "pll4", "pll4_bypass_src", PLL4_CTRL, 0x7f);

	clk[VF610_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_ENET,    "pll5", "pll5_bypass_src", PLL5_CTRL, 0x3);

	clk[VF610_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_AV,      "pll6", "pll6_bypass_src", PLL6_CTRL, 0x7f);

	clk[VF610_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB,     "pll7", "pll7_bypass_src", PLL7_CTRL, 0x1);

	clk[VF610_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB_VF610,     "pll7", "pll7_bypass_src", PLL7_CTRL, 0x2);



	clk[VF610_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", PLL1_CTRL, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);

	clk[VF610_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", PLL2_CTRL, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);

arch/arm/mach-imx/clk.h

+1 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ enum imx_pllv3_type { 
	IMX_PLLV3_GENERIC,

	IMX_PLLV3_SYS,

	IMX_PLLV3_USB,

	IMX_PLLV3_USB_VF610,

	IMX_PLLV3_AV,

	IMX_PLLV3_ENET,

};