Loading drivers/spi/spi-omap2-mcspi.c +134 −146 Original line number Diff line number Diff line Loading @@ -35,6 +35,7 @@ #include <linux/gcd.h> #include <linux/spi/spi.h> #include <linux/gpio.h> #include <linux/platform_data/spi-omap2-mcspi.h> Loading Loading @@ -242,18 +243,28 @@ static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); } static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable) { u32 l; /* The controller handles the inverted chip selects * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert * the inversion from the core spi_set_cs function. */ if (spi->mode & SPI_CS_HIGH) enable = !enable; if (spi->controller_state) { l = mcspi_cached_chconf0(spi); if (cs_active) l |= OMAP2_MCSPI_CHCONF_FORCE; else if (enable) l &= ~OMAP2_MCSPI_CHCONF_FORCE; else l |= OMAP2_MCSPI_CHCONF_FORCE; mcspi_write_chconf0(spi, l); } } static void omap2_mcspi_set_master_mode(struct spi_master *master) { Loading Loading @@ -1011,6 +1022,15 @@ static int omap2_mcspi_setup(struct spi_device *spi) return ret; } if (gpio_is_valid(spi->cs_gpio)) { ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev)); if (ret) { dev_err(&spi->dev, "failed to request gpio\n"); return ret; } gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); } ret = pm_runtime_get_sync(mcspi->dev); if (ret < 0) return ret; Loading Loading @@ -1050,9 +1070,13 @@ static void omap2_mcspi_cleanup(struct spi_device *spi) mcspi_dma->dma_tx = NULL; } } if (gpio_is_valid(spi->cs_gpio)) gpio_free(spi->cs_gpio); } static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) static int omap2_mcspi_work_one(struct omap2_mcspi *mcspi, struct spi_device *spi, struct spi_transfer *t) { /* We only enable one channel at a time -- the one whose message is Loading @@ -1062,18 +1086,14 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) * chipselect with the FORCE bit ... CS != channel enable. */ struct spi_device *spi; struct spi_transfer *t = NULL; struct spi_master *master; struct omap2_mcspi_dma *mcspi_dma; int cs_active = 0; struct omap2_mcspi_cs *cs; struct omap2_mcspi_device_config *cd; int par_override = 0; int status = 0; u32 chconf; spi = m->spi; master = spi->master; mcspi_dma = mcspi->dma_channels + spi->chip_select; cs = spi->controller_state; Loading @@ -1090,18 +1110,17 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) par_override = 1; omap2_mcspi_set_enable(spi, 0); list_for_each_entry(t, &m->transfers, transfer_list) { if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { status = -EINVAL; break; } if (gpio_is_valid(spi->cs_gpio)) omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH); if (par_override || (t->speed_hz != spi->max_speed_hz) || (t->bits_per_word != spi->bits_per_word)) { par_override = 1; status = omap2_mcspi_setup_transfer(spi, t); if (status < 0) break; goto out; if (t->speed_hz == spi->max_speed_hz && t->bits_per_word == spi->bits_per_word) par_override = 0; Loading @@ -1114,12 +1133,6 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); } if (!cs_active) { omap2_mcspi_force_cs(spi, 1); cs_active = 1; } chconf = mcspi_cached_chconf0(spi); chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; Loading @@ -1141,7 +1154,7 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) unsigned count; if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)) (t->len >= DMA_MIN_BYTES)) omap2_mcspi_set_fifo(spi, t, 1); omap2_mcspi_set_enable(spi, 1); Loading @@ -1152,41 +1165,29 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) + OMAP2_MCSPI_TX0); if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)) (t->len >= DMA_MIN_BYTES)) count = omap2_mcspi_txrx_dma(spi, t); else count = omap2_mcspi_txrx_pio(spi, t); m->actual_length += count; if (count != t->len) { status = -EIO; break; } goto out; } if (t->delay_usecs) udelay(t->delay_usecs); /* ignore the "leave it on after last xfer" hint */ if (t->cs_change) { omap2_mcspi_force_cs(spi, 0); cs_active = 0; } omap2_mcspi_set_enable(spi, 0); if (mcspi->fifo_depth > 0) omap2_mcspi_set_fifo(spi, t, 0); } out: /* Restore defaults if they were overriden */ if (par_override) { par_override = 0; status = omap2_mcspi_setup_transfer(spi, NULL); } if (cs_active) omap2_mcspi_force_cs(spi, 0); if (cd && cd->cs_per_word) { chconf = mcspi->ctx.modulctrl; chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE; Loading @@ -1197,32 +1198,27 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) omap2_mcspi_set_enable(spi, 0); if (gpio_is_valid(spi->cs_gpio)) omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH)); if (mcspi->fifo_depth > 0 && t) omap2_mcspi_set_fifo(spi, t, 0); m->status = status; return status; } static int omap2_mcspi_transfer_one_message(struct spi_master *master, struct spi_message *m) static int omap2_mcspi_transfer_one(struct spi_master *master, struct spi_device *spi, struct spi_transfer *t) { struct spi_device *spi; struct omap2_mcspi *mcspi; struct omap2_mcspi_dma *mcspi_dma; struct spi_transfer *t; int status; spi = m->spi; mcspi = spi_master_get_devdata(master); mcspi_dma = mcspi->dma_channels + spi->chip_select; m->actual_length = 0; m->status = 0; list_for_each_entry(t, &m->transfers, transfer_list) { const void *tx_buf = t->tx_buf; void *rx_buf = t->rx_buf; unsigned len = t->len; mcspi = spi_master_get_devdata(master); mcspi_dma = mcspi->dma_channels + spi->chip_select; if ((len && !(rx_buf || tx_buf))) { dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", t->speed_hz, Loading @@ -1230,12 +1226,11 @@ static int omap2_mcspi_transfer_one_message(struct spi_master *master, tx_buf ? "tx" : "", rx_buf ? "rx" : "", t->bits_per_word); status = -EINVAL; goto out; return -EINVAL; } if (m->is_dma_mapped || len < DMA_MIN_BYTES) continue; if (len < DMA_MIN_BYTES) goto skip_dma_map; if (mcspi_dma->dma_tx && tx_buf != NULL) { t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf, Loading @@ -1243,8 +1238,7 @@ static int omap2_mcspi_transfer_one_message(struct spi_master *master, if (dma_mapping_error(mcspi->dev, t->tx_dma)) { dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", 'T', len); status = -EINVAL; goto out; return -EINVAL; } } if (mcspi_dma->dma_rx && rx_buf != NULL) { Loading @@ -1256,19 +1250,12 @@ static int omap2_mcspi_transfer_one_message(struct spi_master *master, if (tx_buf != NULL) dma_unmap_single(mcspi->dev, t->tx_dma, len, DMA_TO_DEVICE); status = -EINVAL; goto out; } return -EINVAL; } } omap2_mcspi_work(mcspi, m); /* spi_finalize_current_message() changes the status inside the * spi_message, save the status here. */ status = m->status; out: spi_finalize_current_message(master); return status; skip_dma_map: return omap2_mcspi_work_one(mcspi, spi, t); } static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) Loading Loading @@ -1347,7 +1334,8 @@ static int omap2_mcspi_probe(struct platform_device *pdev) master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); master->setup = omap2_mcspi_setup; master->auto_runtime_pm = true; master->transfer_one_message = omap2_mcspi_transfer_one_message; master->transfer_one = omap2_mcspi_transfer_one; master->set_cs = omap2_mcspi_set_cs; master->cleanup = omap2_mcspi_cleanup; master->dev.of_node = node; master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ; Loading Loading
drivers/spi/spi-omap2-mcspi.c +134 −146 Original line number Diff line number Diff line Loading @@ -35,6 +35,7 @@ #include <linux/gcd.h> #include <linux/spi/spi.h> #include <linux/gpio.h> #include <linux/platform_data/spi-omap2-mcspi.h> Loading Loading @@ -242,18 +243,28 @@ static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable) mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0); } static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active) static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable) { u32 l; /* The controller handles the inverted chip selects * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert * the inversion from the core spi_set_cs function. */ if (spi->mode & SPI_CS_HIGH) enable = !enable; if (spi->controller_state) { l = mcspi_cached_chconf0(spi); if (cs_active) l |= OMAP2_MCSPI_CHCONF_FORCE; else if (enable) l &= ~OMAP2_MCSPI_CHCONF_FORCE; else l |= OMAP2_MCSPI_CHCONF_FORCE; mcspi_write_chconf0(spi, l); } } static void omap2_mcspi_set_master_mode(struct spi_master *master) { Loading Loading @@ -1011,6 +1022,15 @@ static int omap2_mcspi_setup(struct spi_device *spi) return ret; } if (gpio_is_valid(spi->cs_gpio)) { ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev)); if (ret) { dev_err(&spi->dev, "failed to request gpio\n"); return ret; } gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); } ret = pm_runtime_get_sync(mcspi->dev); if (ret < 0) return ret; Loading Loading @@ -1050,9 +1070,13 @@ static void omap2_mcspi_cleanup(struct spi_device *spi) mcspi_dma->dma_tx = NULL; } } if (gpio_is_valid(spi->cs_gpio)) gpio_free(spi->cs_gpio); } static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) static int omap2_mcspi_work_one(struct omap2_mcspi *mcspi, struct spi_device *spi, struct spi_transfer *t) { /* We only enable one channel at a time -- the one whose message is Loading @@ -1062,18 +1086,14 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) * chipselect with the FORCE bit ... CS != channel enable. */ struct spi_device *spi; struct spi_transfer *t = NULL; struct spi_master *master; struct omap2_mcspi_dma *mcspi_dma; int cs_active = 0; struct omap2_mcspi_cs *cs; struct omap2_mcspi_device_config *cd; int par_override = 0; int status = 0; u32 chconf; spi = m->spi; master = spi->master; mcspi_dma = mcspi->dma_channels + spi->chip_select; cs = spi->controller_state; Loading @@ -1090,18 +1110,17 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) par_override = 1; omap2_mcspi_set_enable(spi, 0); list_for_each_entry(t, &m->transfers, transfer_list) { if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) { status = -EINVAL; break; } if (gpio_is_valid(spi->cs_gpio)) omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH); if (par_override || (t->speed_hz != spi->max_speed_hz) || (t->bits_per_word != spi->bits_per_word)) { par_override = 1; status = omap2_mcspi_setup_transfer(spi, t); if (status < 0) break; goto out; if (t->speed_hz == spi->max_speed_hz && t->bits_per_word == spi->bits_per_word) par_override = 0; Loading @@ -1114,12 +1133,6 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL); } if (!cs_active) { omap2_mcspi_force_cs(spi, 1); cs_active = 1; } chconf = mcspi_cached_chconf0(spi); chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK; chconf &= ~OMAP2_MCSPI_CHCONF_TURBO; Loading @@ -1141,7 +1154,7 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) unsigned count; if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)) (t->len >= DMA_MIN_BYTES)) omap2_mcspi_set_fifo(spi, t, 1); omap2_mcspi_set_enable(spi, 1); Loading @@ -1152,41 +1165,29 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) + OMAP2_MCSPI_TX0); if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) && (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)) (t->len >= DMA_MIN_BYTES)) count = omap2_mcspi_txrx_dma(spi, t); else count = omap2_mcspi_txrx_pio(spi, t); m->actual_length += count; if (count != t->len) { status = -EIO; break; } goto out; } if (t->delay_usecs) udelay(t->delay_usecs); /* ignore the "leave it on after last xfer" hint */ if (t->cs_change) { omap2_mcspi_force_cs(spi, 0); cs_active = 0; } omap2_mcspi_set_enable(spi, 0); if (mcspi->fifo_depth > 0) omap2_mcspi_set_fifo(spi, t, 0); } out: /* Restore defaults if they were overriden */ if (par_override) { par_override = 0; status = omap2_mcspi_setup_transfer(spi, NULL); } if (cs_active) omap2_mcspi_force_cs(spi, 0); if (cd && cd->cs_per_word) { chconf = mcspi->ctx.modulctrl; chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE; Loading @@ -1197,32 +1198,27 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m) omap2_mcspi_set_enable(spi, 0); if (gpio_is_valid(spi->cs_gpio)) omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH)); if (mcspi->fifo_depth > 0 && t) omap2_mcspi_set_fifo(spi, t, 0); m->status = status; return status; } static int omap2_mcspi_transfer_one_message(struct spi_master *master, struct spi_message *m) static int omap2_mcspi_transfer_one(struct spi_master *master, struct spi_device *spi, struct spi_transfer *t) { struct spi_device *spi; struct omap2_mcspi *mcspi; struct omap2_mcspi_dma *mcspi_dma; struct spi_transfer *t; int status; spi = m->spi; mcspi = spi_master_get_devdata(master); mcspi_dma = mcspi->dma_channels + spi->chip_select; m->actual_length = 0; m->status = 0; list_for_each_entry(t, &m->transfers, transfer_list) { const void *tx_buf = t->tx_buf; void *rx_buf = t->rx_buf; unsigned len = t->len; mcspi = spi_master_get_devdata(master); mcspi_dma = mcspi->dma_channels + spi->chip_select; if ((len && !(rx_buf || tx_buf))) { dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n", t->speed_hz, Loading @@ -1230,12 +1226,11 @@ static int omap2_mcspi_transfer_one_message(struct spi_master *master, tx_buf ? "tx" : "", rx_buf ? "rx" : "", t->bits_per_word); status = -EINVAL; goto out; return -EINVAL; } if (m->is_dma_mapped || len < DMA_MIN_BYTES) continue; if (len < DMA_MIN_BYTES) goto skip_dma_map; if (mcspi_dma->dma_tx && tx_buf != NULL) { t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf, Loading @@ -1243,8 +1238,7 @@ static int omap2_mcspi_transfer_one_message(struct spi_master *master, if (dma_mapping_error(mcspi->dev, t->tx_dma)) { dev_dbg(mcspi->dev, "dma %cX %d bytes error\n", 'T', len); status = -EINVAL; goto out; return -EINVAL; } } if (mcspi_dma->dma_rx && rx_buf != NULL) { Loading @@ -1256,19 +1250,12 @@ static int omap2_mcspi_transfer_one_message(struct spi_master *master, if (tx_buf != NULL) dma_unmap_single(mcspi->dev, t->tx_dma, len, DMA_TO_DEVICE); status = -EINVAL; goto out; } return -EINVAL; } } omap2_mcspi_work(mcspi, m); /* spi_finalize_current_message() changes the status inside the * spi_message, save the status here. */ status = m->status; out: spi_finalize_current_message(master); return status; skip_dma_map: return omap2_mcspi_work_one(mcspi, spi, t); } static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi) Loading Loading @@ -1347,7 +1334,8 @@ static int omap2_mcspi_probe(struct platform_device *pdev) master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); master->setup = omap2_mcspi_setup; master->auto_runtime_pm = true; master->transfer_one_message = omap2_mcspi_transfer_one_message; master->transfer_one = omap2_mcspi_transfer_one; master->set_cs = omap2_mcspi_set_cs; master->cleanup = omap2_mcspi_cleanup; master->dev.of_node = node; master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ; Loading