Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 605ae962 authored by Sam Ravnborg's avatar Sam Ravnborg Committed by David S. Miller
Browse files

sparc32: fix coding-style in srmmu.c 



Fix the most annoying issues that distracts me:
- whitespace
- missing space after "if" and "while"
- spaces around operators
and similar simple things.

Signed-off-by: default avatarSam Ravnborg <sam@ravnborg.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 4a049b03

arch/sparc/mm/srmmu.c

+64 −68
Original line number Diff line number Diff line
@@ -420,8 +420,7 @@ static inline void srmmu_mapioaddr(unsigned long physaddr, 
	ptep = pte_offset_kernel(pmdp, virt_addr);

	tmp = (physaddr >> 4) | SRMMU_ET_PTE;



	/*

	 * I need to test whether this is consistent over all

	/* I need to test whether this is consistent over all

	 * sun4m's.  The bus_type represents the upper 4 bits of

	 * 36-bit physical address on the I/O space lines...

	 */
@@ -716,16 +715,14 @@ static void __init srmmu_inherit_prom_mappings(unsigned long start, 
		}

		pmdp = pmd_offset(__nocache_fix(pgdp), start);

		if (srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {

			ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,

							     PTE_SIZE);

			ptep = (pte_t *)__srmmu_get_nocache(PTE_SIZE, PTE_SIZE);

			if (ptep == NULL)

				early_pgtable_allocfail("pte");

			memset(__nocache_fix(ptep), 0, PTE_SIZE);

			pmd_set(__nocache_fix(pmdp), ptep);

		}

		if (what == 1) {

			/*

			 * We bend the rule where all 16 PTPs in a pmd_t point

			/* We bend the rule where all 16 PTPs in a pmd_t point

			 * inside the same PTE page, and we leak a perfectly

			 * good hardware PTE piece. Alternatives seem worse.

			 */
@@ -946,8 +943,7 @@ static void __init init_vac_layout(void) 
		if (!strcmp(node_str, "cpu")) {

			vac_line_size = prom_getint(nd, "cache-line-size");

			if (vac_line_size == -1) {

				prom_printf("can't determine cache-line-size, "

					    "halting.\n");

				prom_printf("can't determine cache-line-size, halting.\n");

				prom_halt();

			}

			cache_lines = prom_getint(nd, "cache-nlines");
@@ -1222,7 +1218,8 @@ static void __cpuinit poke_turbosparc(void) 


	/* Clear any crap from the cache or else... */

	turbosparc_flush_cache_all();

	mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* Temporarily disable I & D caches */

	/* Temporarily disable I & D caches */

	mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE);

	mreg &= ~(TURBOSPARC_PCENABLE);		/* Don't check parity */

	srmmu_set_mmureg(mreg);
@@ -1489,8 +1486,7 @@ static void __init get_srmmu_type(void) 
		return;

	}



	/*

	 * Now Fujitsu TurboSparc. It might happen that it is

	/* Now Fujitsu TurboSparc. It might happen that it is

	 * in Swift emulation mode, so we will check later...

	 */

	if (psr_typ == 0 && psr_vers == 5) {