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Commit 5fea4b52 authored by Srinivas Rao L's avatar Srinivas Rao L
Browse files

ARM: dts: msm: Update MPM interrupt controller config for MSM8917 



Update MPM interrupt controller configuration, soc interrupt parent
as mpm gic,  tlmm interrupt parent as mpm gpio.

Change-Id: Ib9ab5fe412601a2ec832742d4b5ed278430bd0c7
Signed-off-by: default avatarSrinivas Rao L <lsrao@codeaurora.org>
parent c4f52f5e

arch/arm64/boot/dts/qcom/msm8917-pinctrl.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -15,10 +15,11 @@ 
	tlmm: pinctrl@1000000 {

		compatible = "qcom,msm8917-pinctrl";

		reg = <0x1000000 0x300000>;

		interrupts = <0 208 0>;

		interrupts-extended = <&wakegic GIC_SPI 208 IRQ_TYPE_NONE>;

		gpio-controller;

		#gpio-cells = <2>;

		interrupt-controller;

		interrupt-parent = <&wakegpio>;

		#interrupt-cells = <2>;

arch/arm64/boot/dts/qcom/msm8917.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ 
	model = "Qualcomm Technologies, Inc. MSM8917";

	compatible = "qcom,msm8917";

	qcom,msm-id = <303 0x0>, <308 0x0>, <309 0x0>;

	interrupt-parent = <&intc>;

	interrupt-parent = <&wakegic>;



	chosen {

		bootargs = "sched_enable_hmp=1";
@@ -197,19 +197,19 @@ 
	};



	wakegic: wake-gic {

		compatible = "qcom,mpm-gic", "qcom,mpm-gic-msm8937";

		compatible = "qcom,mpm-gic-msm8937", "qcom,mpm-gic";

		interrupts = <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>;

		reg = <0x601d0 0x1000>,

			<0xb011008 0x4>;  /* MSM_APCS_GCC_BASE 4K */

		reg-names = "vmpm", "ipc";

		qcom,num-mpm-irqs = <96>;

		qcom,num-mpm-irqs = <64>;

		interrupt-controller;

		interrupt-parent = <&intc>;

		#interrupt-cells = <3>;

	};



	wakegpio: wake-gpio {

		compatible = "qcom,mpm-gpio", "qcom,mpm-gpio-msm8937";

		compatible = "qcom,mpm-gpio-msm8937", "qcom,mpm-gpio";

		interrupt-controller;

		interrupt-parent = <&intc>;

		#interrupt-cells = <2>;