Loading arch/arm64/boot/dts/qcom/sdm632.dtsi +19 −21 Original line number Diff line number Diff line Loading @@ -792,42 +792,40 @@ &clock_cpu { /delete-property/ vdd-cl-supply; status = "disabled"; compatible = "qcom,cpu-clock-sdm632"; reg = <0xb114000 0x68>, <0xb014000 0x68>, <0xb016000 0x8>, <0xb116000 0x8>, <0xb1d0000 0x8>, <0xb011050 0x8>, <0xb111050 0x8>, <0xb1d1050 0x8>, <0x00a412c 0x8>; <0xb011050 0x8>, <0xb111050 0x8>, <0x00a4124 0x8>; reg-names = "rcgwr-c0-base", "rcgwr-c1-base", "apcs-c1-pll-base", "apcs-c0-pll-base", "apcs-cci-pll-base", "apcs-c1-rcg-base", "apcs-c0-rcg-base", "apcs-cci-rcg-base", "efuse"; "apcs-c1-rcg-base", "apcs-c0-rcg-base", "apcs-cci-rcg-base", "c1-mux", "c0-mux", "efuse"; qcom,num-clusters = <2>; vdd-c0-supply = <&apc0_pwrcl_vreg>; vdd-c1-supply = <&apc1_perfcl_vreg>; vdd-cci-supply = <&apc0_pwrcl_vreg>; clocks = <&clock_gcc clk_xo_a_clk_src>; clock-names = "xo_a"; qcom,speed0-bin-v0-c0 = < 0 0>, < 614400000 1>, < 883200000 2>, < 1036200000 3>, < 1036800000 3>, < 1363200000 4>, < 1563000000 5>, < 1536000000 5>, < 1670400000 6>, < 1785600000 7>; qcom,speed0-bin-v0-c1 = < 0 0>, < 633600000 1>, < 902400000 2>, < 1094400000 3>, < 1401600000 4>, < 1555200000 5>, < 1785600000 6>; < 1094400000 1>, < 1401600000 2>, < 1555200000 3>, < 1785600000 4>; qcom,speed0-bin-v0-cci = < 0 0>, < 307200000 1>, Loading @@ -848,9 +846,9 @@ "cpu0_clk", "cpu4_clk"; clocks = <&clock_cpu clk_a53_cci_clk >, <&clock_cpu clk_a53_pwr_clk >, <&clock_cpu clk_a53_perf_clk >; <&clock_cpu clk_cci_clk >, <&clock_cpu clk_pwr_clk >, <&clock_cpu clk_perf_clk >; qcom,governor-per-policy; Loading @@ -875,7 +873,7 @@ cci_cache: qcom,cci { compatible = "devfreq-simple-dev"; clock-names = "devfreq_clk"; clocks = <&clock_cpu clk_a53_cci_clk >; clocks = <&clock_cpu clk_cci_clk >; governor = "cpufreq"; freq-tbl-khz = < 307200 >, Loading Loading
arch/arm64/boot/dts/qcom/sdm632.dtsi +19 −21 Original line number Diff line number Diff line Loading @@ -792,42 +792,40 @@ &clock_cpu { /delete-property/ vdd-cl-supply; status = "disabled"; compatible = "qcom,cpu-clock-sdm632"; reg = <0xb114000 0x68>, <0xb014000 0x68>, <0xb016000 0x8>, <0xb116000 0x8>, <0xb1d0000 0x8>, <0xb011050 0x8>, <0xb111050 0x8>, <0xb1d1050 0x8>, <0x00a412c 0x8>; <0xb011050 0x8>, <0xb111050 0x8>, <0x00a4124 0x8>; reg-names = "rcgwr-c0-base", "rcgwr-c1-base", "apcs-c1-pll-base", "apcs-c0-pll-base", "apcs-cci-pll-base", "apcs-c1-rcg-base", "apcs-c0-rcg-base", "apcs-cci-rcg-base", "efuse"; "apcs-c1-rcg-base", "apcs-c0-rcg-base", "apcs-cci-rcg-base", "c1-mux", "c0-mux", "efuse"; qcom,num-clusters = <2>; vdd-c0-supply = <&apc0_pwrcl_vreg>; vdd-c1-supply = <&apc1_perfcl_vreg>; vdd-cci-supply = <&apc0_pwrcl_vreg>; clocks = <&clock_gcc clk_xo_a_clk_src>; clock-names = "xo_a"; qcom,speed0-bin-v0-c0 = < 0 0>, < 614400000 1>, < 883200000 2>, < 1036200000 3>, < 1036800000 3>, < 1363200000 4>, < 1563000000 5>, < 1536000000 5>, < 1670400000 6>, < 1785600000 7>; qcom,speed0-bin-v0-c1 = < 0 0>, < 633600000 1>, < 902400000 2>, < 1094400000 3>, < 1401600000 4>, < 1555200000 5>, < 1785600000 6>; < 1094400000 1>, < 1401600000 2>, < 1555200000 3>, < 1785600000 4>; qcom,speed0-bin-v0-cci = < 0 0>, < 307200000 1>, Loading @@ -848,9 +846,9 @@ "cpu0_clk", "cpu4_clk"; clocks = <&clock_cpu clk_a53_cci_clk >, <&clock_cpu clk_a53_pwr_clk >, <&clock_cpu clk_a53_perf_clk >; <&clock_cpu clk_cci_clk >, <&clock_cpu clk_pwr_clk >, <&clock_cpu clk_perf_clk >; qcom,governor-per-policy; Loading @@ -875,7 +873,7 @@ cci_cache: qcom,cci { compatible = "devfreq-simple-dev"; clock-names = "devfreq_clk"; clocks = <&clock_cpu clk_a53_cci_clk >; clocks = <&clock_cpu clk_cci_clk >; governor = "cpufreq"; freq-tbl-khz = < 307200 >, Loading