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Commit 5ee2ae7f authored by Tejun Heo's avatar Tejun Heo Committed by Jeff Garzik
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jmicron ATA: reimplement jmicron ATA quirk 



Reimplement jmicron ATA quirk.

* renamed to quirk_jmicron_ata()
* quirk is invoked only for the affected controllers
* programming is stricter.  e.g. conf5 bit24 is cleared if
  unnecessary.
* code factored for readability
* JMB360 and JMB368 are programmed into proper mode

Verified on JMB360, 363 and 368.

Signed-off-by: default avatarTejun Heo <htejun@gmail.com>
Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
parent 960627b7

drivers/pci/quirks.c

+50 −30
Original line number Diff line number Diff line
@@ -1218,45 +1218,65 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_a 
 *	do this early on to make the additional device appear during

 *	the PCI scanning.

 */



static void quirk_jmicron_dualfn(struct pci_dev *pdev)

static void quirk_jmicron_ata(struct pci_dev *pdev)

{

	u32 conf;

	u32 conf1, conf5;

	u8 hdr;



	/* Only poke fn 0 */

	if (PCI_FUNC(pdev->devfn))

		return;



	pci_read_config_dword(pdev, 0x40, &conf1);

	pci_read_config_dword(pdev, 0x80, &conf5);



	conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */

	conf5 &= ~(1 << 24);  /* Clear bit 24 */



	switch (pdev->device) {

	case PCI_DEVICE_ID_JMICRON_JMB360:

		/* The controller should be in single function ahci mode */

		conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */

		break;



	case PCI_DEVICE_ID_JMICRON_JMB365:

	case PCI_DEVICE_ID_JMICRON_JMB366:

		/* Redirect IDE second PATA port to the right spot */

			pci_read_config_dword(pdev, 0x80, &conf);

			conf |= (1 << 24);

		conf5 |= (1 << 24);

		/* Fall through */

			pci_write_config_dword(pdev, 0x80, conf);

	case PCI_DEVICE_ID_JMICRON_JMB361:

	case PCI_DEVICE_ID_JMICRON_JMB363:

			pci_read_config_dword(pdev, 0x40, &conf);

		/* Enable dual function mode, AHCI on fn 0, IDE fn1 */

		/* Set the class codes correctly and then direct IDE 0 */

			conf &= ~0x000FF200; /* Clear bit 9 and 12-19 */

			conf |=  0x00C2A102; /* Set 1, 8, 13, 15, 17, 22, 23 */

			pci_write_config_dword(pdev, 0x40, conf);

		conf1 |= 0x00C2A102; /* Set 1, 8, 13, 15, 17, 22, 23 */

		break;



			/* Reconfigure so that the PCI scanner discovers the

			   device is now multifunction */

	case PCI_DEVICE_ID_JMICRON_JMB368:

		/* The controller should be in single function IDE mode */

		conf1 |= 0x00C00000; /* Set 22, 23 */

		break;

	}



	pci_write_config_dword(pdev, 0x40, conf1);

	pci_write_config_dword(pdev, 0x80, conf5);



	/* Update pdev accordingly */

	pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);

	pdev->hdr_type = hdr & 0x7f;

	pdev->multifunction = !!(hdr & 0x80);



			break;

	}

}

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, quirk_jmicron_dualfn);

DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, quirk_jmicron_dualfn);

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);

DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);

DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);

DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);

DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);

DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);

DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);



#endif