Commit 5d7e5d15 authored Apr 07, 2017 by Xiaonian Wang Committed by Subhash Jadavani Apr 26, 2017

ARM: dts: msm: enable SDR104 workaround for SDM845



On SDM845, SDR104 mode might be unstable causing CRC error on
the interface. So we need a workaround which would skip printing register
dumps on CRC errors and also downgrade bus speed mode to SDR50/DDR50 in
case of continuos CRC errors. This patch enables "qcom,sdr104-wa" property
to enable this workaround.

Change-Id: Ib2dbf974d1312c00ca22a114f0b9e8130624090c
Signed-off-by: Xiaonian Wang <xiaonian@codeaurora.org>

parent cd13656b

arch/arm64/boot/dts/qcom/sdm845.dtsi

+2 −0

Original line number	Diff line number	Diff line
		@@ -1263,6 +1263,8 @@
		qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
		100000000 200000000 4294967295>;

		qcom,sdr104-wa;

		qcom,devfreq,freq-table = <50000000 200000000>;
		clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>,
		<&clock_gcc GCC_SDCC2_APPS_CLK>;