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Commit 5d641d47 authored by Shashank Babu Chinta Venkata's avatar Shashank Babu Chinta Venkata Committed by Gerrit - the friendly Code Review server
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drm/msm/sde: read MDSS registers for current configuration 



During SDE hardware initialization, read MDP registers
to check the current MDSS configuration. This information
will be used to update software structures when
continuous splash feature is enabled.

Change-Id: Ieb9e80e67a163a3197c882b624a05b1409383aaf
Signed-off-by: default avatarChandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: default avatarShashank Babu Chinta Venkata <sbchin@codeaurora.org>
parent 7d608734

drivers/gpu/drm/msm/sde/sde_hw_ctl.c

+21 −0
Original line number Diff line number Diff line
@@ -616,6 +616,27 @@ static void _setup_ctl_ops(struct sde_hw_ctl_ops *ops, 
	}

};



#define CTL_BASE_OFFSET	0x2000

#define CTL_TOP_OFFSET(index) (CTL_BASE_OFFSET + (0x200 * (index)) + CTL_TOP)



void sde_get_ctl_top_for_cont_splash(void __iomem *mmio,

		struct ctl_top *top, int index)

{

	if (!mmio || !top) {

		SDE_ERROR("invalid input parameters\n");

		return;

	}



	top->value = readl_relaxed(mmio + CTL_TOP_OFFSET(index));

	top->intf_sel = (top->value >> 4) & 0xf;

	top->pp_sel = (top->value >> 8) & 0x7;

	top->dspp_sel = (top->value >> 11) & 0x3;

	top->mode_sel = (top->value >> 17) & 0x1;



	SDE_DEBUG("ctl[%d]_top->0x%x,pp_sel=0x%x,dspp_sel=0x%x,intf_sel=0x%x\n",

	       index, top->value, top->pp_sel, top->dspp_sel, top->intf_sel);

}



static struct sde_hw_blk_ops sde_hw_ops = {

	.start = NULL,

	.stop = NULL,

drivers/gpu/drm/msm/sde/sde_hw_ctl.h

+9 −0
Original line number Diff line number Diff line
@@ -253,6 +253,15 @@ struct sde_hw_ctl { 
	struct sde_hw_ctl_ops ops;

};



/**

 * sde_get_ctl_top_for_cont_splash - retrieve the current LM blocks

 * @mmio: mapped register io address of MDP

 * @top: pointer to the current "ctl_top" structure thats needs update

 * @index: ctl_top index

 */

void sde_get_ctl_top_for_cont_splash(void __iomem *mmio,

		struct ctl_top *top, int index);



/**

 * sde_hw_ctl - convert base object sde_hw_base to container

 * @hw: Pointer to base hardware block

drivers/gpu/drm/msm/sde/sde_hw_lm.c

+37 −0
Original line number Diff line number Diff line
@@ -278,6 +278,43 @@ static void _setup_mixer_ops(struct sde_mdss_cfg *m, 
	}

};



#define CTL_BASE_OFFSET	0x2000

#define CTL_TOP_LM_OFFSET(index, lm)	\

	(CTL_BASE_OFFSET + (0x200 * index) + (lm * 0x4))



int sde_get_ctl_lm_for_cont_splash(void __iomem *mmio, int max_lm_cnt,

		u8 lm_cnt, u8 *lm_ids, struct ctl_top *top, int index)

{

	int j;

	struct sde_splash_lm_hw *lm;



	if (!mmio || !top || !lm_ids) {

		SDE_ERROR("invalid input parameters\n");

		return 0;

	}



	lm = top->lm;

	for (j = 0; j < max_lm_cnt; j++) {

		lm[top->ctl_lm_cnt].lm_reg_value = readl_relaxed(mmio

			      + CTL_TOP_LM_OFFSET(index, j));

		SDE_DEBUG("ctl[%d]_top --> lm[%d]=0x%x, j=%d\n",

			index, top->ctl_lm_cnt,

			lm[top->ctl_lm_cnt].lm_reg_value, j);

		SDE_DEBUG("lm_cnt = %d\n", lm_cnt);

		if (lm[top->ctl_lm_cnt].lm_reg_value) {

			lm[top->ctl_lm_cnt].ctl_id = index;

			lm_ids[lm_cnt++] = j + LM_0;

			lm[top->ctl_lm_cnt].lm_id = j + LM_0;

			SDE_DEBUG("ctl_id=%d, lm[%d].lm_id = %d\n",

				lm[top->ctl_lm_cnt].ctl_id,

				top->ctl_lm_cnt,

				lm[top->ctl_lm_cnt].lm_id);

			top->ctl_lm_cnt++;

		}

	}

	return top->ctl_lm_cnt;

}



static struct sde_hw_blk_ops sde_hw_ops = {

	.start = NULL,

	.stop = NULL,

drivers/gpu/drm/msm/sde/sde_hw_lm.h

+13 −0
Original line number Diff line number Diff line
@@ -116,6 +116,19 @@ static inline struct sde_hw_mixer *to_sde_hw_mixer(struct sde_hw_blk *hw) 
	return container_of(hw, struct sde_hw_mixer, base);

}



/**

 * sde_get_ctl_lm_for_cont_splash - retrieve the current LM blocks

 * @mmio: mapped register io address of MDP

 * @max_lm_cnt: number of LM blocks supported in the hw

 * @lm_cnt: number of LM blocks already active

 * @lm_ids: pointer to store the active LM block IDs

 * @top: pointer to the current "ctl_top" structure

 * @index: ctl_top index

 * return: number of active LM blocks for this CTL block

 */

int sde_get_ctl_lm_for_cont_splash(void __iomem *mmio, int max_lm_cnt,

		u8 lm_cnt, u8 *lm_ids, struct ctl_top *top, int index);



/**

 * sde_hw_lm_init(): Initializes the mixer hw driver object.

 * should be called once before accessing every mixer.

drivers/gpu/drm/msm/sde/sde_hw_mdss.h

+53 −0
Original line number Diff line number Diff line
@@ -535,4 +535,57 @@ struct sde_hw_dim_layer { 
	struct sde_rect rect;

};



/**

 * struct sde_splash_lm_hw - Struct contains LM block properties

 * @lm_id:	stores the current LM ID

 * @ctl_id:	stores the current CTL ID associated with the LM.

 * @lm_reg_value:Store the LM block register value

 */

struct sde_splash_lm_hw {

	u8 lm_id;

	u8 ctl_id;

	u32 lm_reg_value;

};



/**

 * struct ctl_top - Struct contains CTL block properties

 * @value:	Store the CTL block register value

 * @mode_sel:	stores the mode selected in the CTL block

 * @dspp_sel:	stores the dspp selected in the CTL block

 * @pp_sel:	stores the pp selected in the CTL block

 * @intf_sel:	stores the intf selected in the CTL block

 * @lm:		Pointer to store the list of LMs in the CTL block

 * @ctl_lm_cnt:	stores the active number of MDSS "LM" blocks in the CTL block

 */

struct ctl_top {

	u32 value;

	u8 mode_sel;

	u8 dspp_sel;

	u8 pp_sel;

	u8 intf_sel;

	struct sde_splash_lm_hw lm[LM_MAX - LM_0];

	u8 ctl_lm_cnt;

};



/**

 * struct sde_splash_data - Struct contains details of continuous splash

 *	initial pipeline configuration.

 * @top:	struct ctl_top objects

 * @ctl_ids:	stores the valid MDSS ctl block ids for the current mode

 * @lm_ids:	stores the valid MDSS layer mixer block ids for the current mode

 * @dsc_ids:	stores the valid MDSS DSC block ids for the current mode

 * @ctl_top_cnt:stores the active number of MDSS "top" blks of the current mode

 * @lm_cnt:	stores the active number of MDSS "LM" blks for the current mode

 * @dsc_cnt:	stores the active number of MDSS "dsc" blks for the current mode

 */

struct sde_splash_data {

	struct ctl_top top[CTL_MAX - CTL_0];

	u8 ctl_ids[CTL_MAX - CTL_0];

	u8 lm_ids[LM_MAX - LM_0];

	u8 dsc_ids[DSC_MAX - DSC_0];

	u8 ctl_top_cnt;

	u8 lm_cnt;

	u8 dsc_cnt;

};



#endif  /* _SDE_HW_MDSS_H */