Merge "ARM: dts: msm: Add GPU speed bin support for QM215"

					308570000 270000000 200000000>;

	};

};

/* GPU overrides */

&msm_gpu {

	qcom,gpu-speed-bin = <0x0164 0x00000600 9>;

	/delete-property/qcom,gpu-speed-bin-vectors;

	/delete-node/qcom,gpu-pwrlevel-bins;

	qcom,gpu-pwrlevel-bins {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible="qcom,gpu-pwrlevel-bins";

		qcom,gpu-pwrlevels-0 {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,speed-bin = <0>;

			qcom,initial-pwrlevel = <3>;

			/* TURBO */

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <598000000>;

				qcom,bus-freq = <7>;

				qcom,bus-min = <7>;

				qcom,bus-max = <7>;

			};

			/* NOM+ */

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <523200000>;

				qcom,bus-freq = <6>;

				qcom,bus-min = <5>;

				qcom,bus-max = <7>;

			};

			/* NOM */

			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <484800000>;

				qcom,bus-freq = <5>;

				qcom,bus-min = <4>;

				qcom,bus-max = <6>;

			};

			/* SVS+ */

			qcom,gpu-pwrlevel@3 {

				reg = <3>;

				qcom,gpu-freq = <400000000>;

				qcom,bus-freq = <4>;

				qcom,bus-min = <3>;

				qcom,bus-max = <5>;

			};

			/* SVS */

			qcom,gpu-pwrlevel@4 {

				reg = <4>;

				qcom,gpu-freq = <270000000>;

				qcom,bus-freq = <3>;

				qcom,bus-min = <1>;

				qcom,bus-max = <3>;

			};

			/* XO */

			qcom,gpu-pwrlevel@5 {

				reg = <5>;

				qcom,gpu-freq = <19200000>;

				qcom,bus-freq = <0>;

				qcom,bus-min = <0>;

				qcom,bus-max = <0>;

			};

		};

		qcom,gpu-pwrlevels-1 {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,speed-bin = <1>;

			qcom,initial-pwrlevel = <2>;

			/* NOM+ */

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <500000000>;

				qcom,bus-freq = <7>;

				qcom,bus-min = <6>;

				qcom,bus-max = <7>;

			};

			/* NOM */

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <465000000>;

				qcom,bus-freq = <7>;

				qcom,bus-min = <5>;

				qcom,bus-max = <7>;

			};

			/* SVS+ */

			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <400000000>;

				qcom,bus-freq = <4>;

				qcom,bus-min = <3>;

				qcom,bus-max = <5>;

			};

			/* SVS */

			qcom,gpu-pwrlevel@3 {

				reg = <3>;

				qcom,gpu-freq = <270000000>;

				qcom,bus-freq = <3>;

				qcom,bus-min = <1>;

				qcom,bus-max = <3>;

			};

			/* XO */

			qcom,gpu-pwrlevel@4 {

				reg = <4>;

				qcom,gpu-freq = <19200000>;

				qcom,bus-freq = <0>;

				qcom,bus-min = <0>;

				qcom,bus-max = <0>;

			};

		};

		qcom,gpu-pwrlevels-2 {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,speed-bin = <2>;

			qcom,initial-pwrlevel = <1>;

			/* NOM */

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <465000000>;

				qcom,bus-freq = <7>;

				qcom,bus-min = <5>;

				qcom,bus-max = <7>;

			};

			/* SVS+ */

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <400000000>;

				qcom,bus-freq = <4>;

				qcom,bus-min = <3>;

				qcom,bus-max = <5>;

			};

			/* SVS */

			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <270000000>;

				qcom,bus-freq = <3>;

				qcom,bus-min = <1>;

				qcom,bus-max = <3>;

			};

			/* XO */

			qcom,gpu-pwrlevel@3 {

				reg = <3>;

				qcom,gpu-freq = <19200000>;

				qcom,bus-freq = <0>;

				qcom,bus-min = <0>;

				qcom,bus-max = <0>;

			};

		};

		qcom,gpu-pwrlevels-3 {

			#address-cells = <1>;

			#size-cells = <0>;

			qcom,speed-bin = <3>;

			qcom,initial-pwrlevel = <0>;

			/* SVS+ */

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <400000000>;

				qcom,bus-freq = <4>;

				qcom,bus-min = <3>;

				qcom,bus-max = <6>;

			};

			/* SVS */

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <270000000>;

				qcom,bus-freq = <3>;

				qcom,bus-min = <1>;

				qcom,bus-max = <3>;

			};

			/* XO */

			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <19200000>;

				qcom,bus-freq = <0>;

				qcom,bus-min = <0>;

				qcom,bus-max = <0>;

			};

		};

	};

};