[ARM] pxa: add missing ACCR bit definitions to pxa3xx-regs.h

#define CKENB		__REG(0x41340010)	/* B Clock Enable Register */

#define AC97_DIV	__REG(0x41340014)	/* AC97 clock divisor value register */

#define ACCR_XPDIS		(1 << 31)	/* Core PLL Output Disable */

#define ACCR_SPDIS		(1 << 30)	/* System PLL Output Disable */

#define ACCR_D0CS		(1 << 26)	/* D0 Mode Clock Select */

#define ACCR_PCCE		(1 << 11)	/* Power Mode Change Clock Enable */

#define ACCR_DDR_D0CS		(1 << 7)	/* DDR SDRAM clock frequency in D0CS (PXA31x only) */

#define ACCR_SMCFS_MASK		(0x7 << 23)	/* Static Memory Controller Frequency Select */

#define ACCR_SFLFS_MASK		(0x3 << 18)	/* Frequency Select for Internal Memory Controller */

#define ACCR_XSPCLK_MASK	(0x3 << 16)	/* Core Frequency during Frequency Change */

#define ACCR_HSS_MASK		(0x3 << 14)	/* System Bus-Clock Frequency Select */

#define ACCR_DMCFS_MASK		(0x3 << 12)	/* Dynamic Memory Controller Clock Frequency Select */

#define ACCR_XN_MASK		(0x7 << 8)	/* Core PLL Turbo-Mode-to-Run-Mode Ratio */

#define ACCR_XL_MASK		(0x1f)		/* Core PLL Run-Mode-to-Oscillator Ratio */

#define ACCR_SMCFS(x)		(((x) & 0x7) << 23)

#define ACCR_SFLFS(x)		(((x) & 0x3) << 18)

#define ACCR_XSPCLK(x)		(((x) & 0x3) << 16)

#define ACCR_HSS(x)		(((x) & 0x3) << 14)

#define ACCR_DMCFS(x)		(((x) & 0x3) << 12)

#define ACCR_XN(x)		(((x) & 0x7) << 8)

#define ACCR_XL(x)		((x) & 0x1f)

/*

 * Clock Enable Bit

 */