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Commit 5c1c071a authored by Thierry Reding's avatar Thierry Reding
Browse files

drm/tegra: hdmi: Name register fields consistently 



Name the fields of the SOR_SEQ_CTL register consistently.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 375e1184

drivers/gpu/drm/tegra/hdmi.c

+1 −1
Original line number Diff line number Diff line
@@ -952,7 +952,7 @@ static void tegra_hdmi_encoder_mode_set(struct drm_encoder *encoder, 
	}



	tegra_hdmi_writel(hdmi,

			  SOR_SEQ_CTL_PU_PC(0) |

			  SOR_SEQ_PU_PC(0) |

			  SOR_SEQ_PU_PC_ALT(0) |

			  SOR_SEQ_PD_PC(8) |

			  SOR_SEQ_PD_PC_ALT(8),

drivers/gpu/drm/tegra/hdmi.h

+1 −1
Original line number Diff line number Diff line
@@ -201,7 +201,7 @@ 
#define HDMI_NV_PDISP_SOR_CRCB					0x5d

#define HDMI_NV_PDISP_SOR_BLANK					0x5e

#define HDMI_NV_PDISP_SOR_SEQ_CTL				0x5f

#define SOR_SEQ_CTL_PU_PC(x) (((x) & 0xf) <<  0)

#define SOR_SEQ_PU_PC(x)     (((x) & 0xf) <<  0)

#define SOR_SEQ_PU_PC_ALT(x) (((x) & 0xf) <<  4)

#define SOR_SEQ_PD_PC(x)     (((x) & 0xf) <<  8)

#define SOR_SEQ_PD_PC_ALT(x) (((x) & 0xf) << 12)