Merge branch 'mdss-final-replay' into msm-4.4

SDE Rotator

SDE rotator is a v4l2 rotator driver, which manages the rotator hw

block inside the Snapdragon Display Engine (or Mobile Display Subsystem)

Required properties

- compatible:		Must be "qcom,sde-rotator".

- reg:			offset and length of the register set for the device.

- reg-names:		names to refer to register sets related to this device

- interrupt-parent:	phandle for the interrupt controller that

			services interrupts for this device.

- interrupts:		Interrupt associated with rotator.

- <name>-supply:	Phandle for <name> regulator device node.

- qcom,supply-names:	names to refer to regulator device node.

- clocks:		List of Phandles for clock device nodes

			needed by the device.

- clock-names:		List of clock names needed by the device.

Bus Scaling Data:

- qcom,msm-bus,name:		String property describing rotator client.

- qcom,msm-bus,num-cases:	This is the the number of Bus Scaling use cases

				defined in the vectors property. This must be

				set to <3> for rotator driver where use-case 0 is

				used to take off rotator BW votes from the system.

				And use-case 1 & 2 are used in ping-pong fashion

				to generate run-time BW requests.

- qcom,msm-bus,num-paths:	This represents the number of paths in each

				Bus Scaling Usecase. This value depends on

				how many number of AXI master ports are

				dedicated to rotator for particular chipset.

- qcom,msm-bus,vectors-KBps:	* A series of 4 cell properties, with a format

				of (src, dst, ab, ib) which is defined at

				Documentation/devicetree/bindings/arm/msm/msm_bus.txt

				* Current values of src & dst are defined at

				include/linux/msm-bus-board.h

				src values allowed for rotator are:

					25 = MSM_BUS_MASTER_ROTATOR

				dst values allowed for rotator are:

					512 = MSM_BUS_SLAVE_EBI_CH0

				ab: Represents aggregated bandwidth.

				ib: Represents instantaneous bandwidth.

				* Total number of 4 cell properties will be

				(number of use-cases * number of paths).

				* These values will be overridden by the driver

				based on the run-time requirements. So initial

				ab and ib values defined here are random and

				bare no logic except for the use-case 0 where ab

				and ib values needs to be 0.

				* Define realtime vector properties followed by

				non-realtime vector properties.

Optional properties

- qcom,rot-vbif-settings: 	Array with key-value pairs of constant VBIF register

				settings used to setup MDSS QoS for optimum performance.

				The key used should be offset from "rot_vbif_phys" register

				defined in reg property.

- qcom,mdss-rot-block-size:	This integer value indicates the size of a memory block

				(in pixels) to be used by the rotator. If this property

				is not specified, then a default value of 128 pixels

				would be used.

- qcom,mdss-highest-bank-bit:	This integer value indicate tile format as opposed to usual

				linear format. The value tells the GPU highest memory

				bank bit used.

- qcom,mdss-default-ot-wr-limit: This integer value indicates maximum number of pending

				writes that can be allowed on each WR xin.

				This value can be used to reduce the pending writes

				limit and can be tuned to match performance

				requirements depending upon system state.

				Some platforms require a dynamic ot limiting in

				some cases. Setting this default ot write limit

				will enable this dynamic limiting for the write

				operations in the platforms that require these

				limits.

- qcom,mdss-default-ot-rd-limit: This integer value indicates the default number of pending

				reads that can be allowed on each RD xin.

				Some platforms require a dynamic ot limiting in

				some cases. Setting this default ot read limit

				will enable this dynamic limiting for the read

				operations in the platforms that require these

				limits.

- qcom,mdss-rot-vbif-qos-setting: This array is used to program vbif qos remapper register

				  priority for rotator clients.

- qcom,mdss-rot-mode:		This is integer value indicates operation mode

				of the rotator device

Subnode properties:

- compatible:		Compatible name used in smmu v2.

			smmu_v2 names should be:

			"qcom,smmu_sde_rot_unsec"- smmu context bank device for

						unsecure rotation domain.

			"qcom,smmu_sde_rot_sec"	- smmu context bank device for

						secure rotation domain.

- iommus:		specifies the SID's used by this context bank

- gdsc-mdss-supply: 	Phandle for mdss supply regulator device node.

- clocks:		List of Phandles for clock device nodes

			needed by the device.

- clock-names:		List of clock names needed by the device.

Example:

	mdss_rotator: qcom,mdss_rotator {

		compatible = "qcom,sde_rotator";

		reg = <0xfd900000 0x22100>,

			<0xfd925000 0x1000>;

		reg-names = "mdp_phys", "rot_vbif_phys";

		interrupt-parent = <&mdss_mdp>;

		interrupts = <2 0>;

		qcom,mdss-mdp-reg-offset = <0x00001000>;

		rot-vdd-supply = <&gdsc_mdss>;

		qcom,supply-names = "rot-vdd";

		clocks = <&clock_mmss clk_mmss_mdss_ahb_clk>,

			<&clock_mmss clk_mmss_mdss_rot_clk>;

		clock-names = "iface_clk", "rot_core_clk";

		qcom,mdss-highest-bank-bit = <0x2>;

		/* Bus Scale Settings */

		qcom,msm-bus,name = "mdss_rotator";

		qcom,msm-bus,num-cases = <3>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

			<25 512 0 0>,

			<25 512 0 6400000>,

			<25 512 0 6400000>;

		/* VBIF QoS remapper settings*/

		qcom,mdss-rot-vbif-qos-setting = <1 1 1 1>;

		qcom,mdss-default-ot-rd-limit = <8>;

		qcom,mdss-default-ot-wr-limit = <16>;

		smmu_rot_unsec: qcom,smmu_rot_unsec_cb {

			compatible = "qcom,smmu_sde_rot_unsec";

			iommus = <&mdp_smmu 0xe00>;

			gdsc-mdss-supply = <&gdsc_bimc_smmu>;

			clocks = <&clock_mmss clk_bimc_smmu_ahb_clk>,

				<&clock_mmss clk_bimc_smmu_axi_clk>;

			clock-names = "rot_ahb_clk", "rot_axi_clk";

		};

		smmu_sde_rot_sec: qcom,smmu_sde_rot_sec_cb {

			compatible = "qcom,smmu_sde_rot_sec";

			iommus = <&mmss_smmu 0xe01>;

			gdsc-mdss-supply = <&gdsc_bimc_smmu>;

			clocks = <&clock_mmss clk_bimc_smmu_ahb_clk>,

				<&clock_mmss clk_bimc_smmu_axi_clk>;

			clock-names = "rot_ahb_clk", "rot_axi_clk";

		};

	};

	struct mdss_pll_resources *pll = clk->priv;

	struct dsi_pll_db *pdb;

	struct dsi_pll_output *pout;

	int rc;

	u32 n1div = 0;

	rc = mdss_pll_resource_enable(pll, true);

	if (rc) {

		pr_err("Failed to enable mdss dsi pll resources\n");

		return rc;

	}

	pdb = (struct dsi_pll_db *)pll->priv;

	pout = &pdb->out;

	pout->pll_postdiv = 1;	/* fixed, divided by 1 */

	pout->pll_n1div  = div;

	n1div = MDSS_PLL_REG_R(pll->pll_base, DSIPHY_CMN_CLK_CFG0);

	n1div &= ~0xf;

	n1div |= (div & 0xf);

	MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_CLK_CFG0, n1div);

	/* ensure n1 divider is programed */

	wmb();

	pr_debug("ndx=%d div=%d postdiv=%x n1div=%x\n",

			pll->index, div, pout->pll_postdiv, pout->pll_n1div);

	/* registers committed at pll_db_commit_8996() */

	mdss_pll_resource_enable(pll, false);

	return 0;

}

int dsi_pll_clock_register_8996(struct platform_device *pdev,

				struct mdss_pll_resources *pll_res)

{

	int rc, ndx;

	int rc = 0, ndx;

	int const ssc_freq_default = 31500; /* default h/w recommended value */

	int const ssc_ppm_default = 5000; /* default h/w recommended value */

	struct dsi_pll_db *pdb;

#define HDMI_300MHZ_BIT_CLK_HZ                   300000000

#define HDMI_282MHZ_BIT_CLK_HZ                   282000000

#define HDMI_250MHZ_BIT_CLK_HZ                   250000000

#define HDMI_KHZ_TO_HZ                           1000

/* PLL REGISTERS */

#define QSERDES_COM_ATB_SEL1                     (0x000)

	cfg->com_lock_cmp1_mode0 = (pll_cmp & 0xFF);

	cfg->com_lock_cmp2_mode0 = ((pll_cmp & 0xFF00) >> 8);

	cfg->com_lock_cmp3_mode0 = ((pll_cmp & 0x30000) >> 16);

	cfg->com_lock_cmp_en = 0x0;

	cfg->com_lock_cmp_en = 0x04;

	cfg->com_core_clk_en = 0x2C;

	cfg->com_coreclk_div = HDMI_CORECLK_DIV;

	cfg->phy_mode = (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) ? 0x10 : 0x0;

	return hdmi_8996_vco_enable(c, HDMI_VERSION_8996_V3_1_8);

}

static int hdmi_8996_vco_get_lock_range(struct clk *c, unsigned long pixel_clk)

{

	u32 rng = 64, cmp_cnt = 1024;

	u32 coreclk_div = 5, clks_pll_divsel = 2;

	u32 vco_freq, vco_ratio, ppm_range;

	u64 bclk;

	struct hdmi_8996_v3_post_divider pd;

	bclk = ((u64)pixel_clk) * HDMI_BIT_CLK_TO_PIX_CLK_RATIO;

	DEV_DBG("%s: rate=%ld\n", __func__, pixel_clk);

	if (hdmi_8996_v3_get_post_div(&pd, bclk) ||

		pd.vco_ratio <= 0 || pd.vco_freq <= 0) {

		DEV_ERR("%s: couldn't get post div\n", __func__);

		return -EINVAL;

	}

	do_div(pd.vco_freq, HDMI_KHZ_TO_HZ * HDMI_KHZ_TO_HZ);

	vco_freq  = (u32) pd.vco_freq;

	vco_ratio = (u32) pd.vco_ratio;

	DEV_DBG("%s: freq %d, ratio %d\n", __func__,

		vco_freq, vco_ratio);

	ppm_range = (rng * HDMI_REF_CLOCK) / cmp_cnt;

	ppm_range /= vco_freq / vco_ratio;

	ppm_range *= coreclk_div * clks_pll_divsel;

	DEV_DBG("%s: ppm range: %d\n", __func__, ppm_range);

	return ppm_range;

}

static int hdmi_8996_vco_rate_atomic_update(struct clk *c,

	unsigned long rate, u32 ver)

{

	struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c);

	struct mdss_pll_resources *io = vco->priv;

	void __iomem *pll;

	struct hdmi_8996_phy_pll_reg_cfg cfg = {0};

	int rc = 0;

	rc = hdmi_8996_calculate(rate, &cfg, ver);

	if (rc) {

		DEV_ERR("%s: PLL calculation failed\n", __func__);

		goto end;

	}

	pll = io->pll_base;

	MDSS_PLL_REG_W(pll, QSERDES_COM_DEC_START_MODE0,

		       cfg.com_dec_start_mode0);

	MDSS_PLL_REG_W(pll, QSERDES_COM_DIV_FRAC_START1_MODE0,

		       cfg.com_div_frac_start1_mode0);

	MDSS_PLL_REG_W(pll, QSERDES_COM_DIV_FRAC_START2_MODE0,

		       cfg.com_div_frac_start2_mode0);

	MDSS_PLL_REG_W(pll, QSERDES_COM_DIV_FRAC_START3_MODE0,

		       cfg.com_div_frac_start3_mode0);

	MDSS_PLL_REG_W(pll, QSERDES_COM_FREQ_UPDATE, 0x01);

	MDSS_PLL_REG_W(pll, QSERDES_COM_FREQ_UPDATE, 0x00);

	DEV_DBG("%s: updated to rate %ld\n", __func__, rate);

end:

	return rc;

}

static int hdmi_8996_vco_set_rate(struct clk *c, unsigned long rate, u32 ver)

{

	struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c);

	struct mdss_pll_resources *io = vco->priv;

	void __iomem		*pll_base;

	void __iomem		*phy_base;

	unsigned int set_power_dwn = 0;

	int rc;

	bool atomic_update = false;

	int rc, pll_lock_range;

	rc = mdss_pll_resource_enable(io, true);

	if (rc) {

		return rc;

	}

	if (io->pll_on)

		set_power_dwn = 1;

	DEV_DBG("%s: rate %ld\n", __func__, rate);

	if (MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_C_READY_STATUS) & BIT(0) &&

		MDSS_PLL_REG_R(io->phy_base, HDMI_PHY_STATUS) & BIT(0)) {

		pll_lock_range = hdmi_8996_vco_get_lock_range(c, vco->rate);

		if (pll_lock_range > 0 && vco->rate) {

			u32 range_limit;

			range_limit  = vco->rate *

				(pll_lock_range / HDMI_KHZ_TO_HZ);

			range_limit /= HDMI_KHZ_TO_HZ;

			DEV_DBG("%s: range limit %d\n", __func__, range_limit);

	pll_base = io->pll_base;

	phy_base = io->phy_base;

			if (abs(rate - vco->rate) < range_limit)

				atomic_update = true;

		}

	}

	DEV_DBG("HDMI PIXEL CLK rate=%ld\n", rate);

	if (io->pll_on && !atomic_update)

		set_power_dwn = 1;

	if (atomic_update) {

		hdmi_8996_vco_rate_atomic_update(c, rate, ver);

	} else {

		rc = hdmi_8996_phy_pll_set_clk_rate(c, rate, ver);

		if (rc)

			DEV_ERR("%s: Failed to set clk rate\n", __func__);

	}

	mdss_pll_resource_enable(io, false);

	return hdmi_8996_vco_set_rate(c, rate, HDMI_VERSION_8996_V3_1_8);

}

static unsigned long hdmi_get_hsclk_sel_divisor(unsigned long hsclk_sel)

{

	unsigned long divisor;

	switch (hsclk_sel) {

	case 0:

		divisor = 2;

		break;

	case 1:

		divisor = 6;

		break;

	case 2:

		divisor = 10;

		break;

	case 3:

		divisor = 14;

		break;

	case 4:

		divisor = 3;

		break;

	case 5:

		divisor = 9;

		break;

	case 6:

	case 13:

		divisor = 15;

		break;

	case 7:

		divisor = 21;

		break;

	case 8:

		divisor = 4;

		break;

	case 9:

		divisor = 12;

		break;

	case 10:

		divisor = 20;

		break;

	case 11:

		divisor = 28;

		break;

	case 12:

		divisor = 5;

		break;

	case 14:

		divisor = 25;

		break;

	case 15:

		divisor = 35;

		break;

	default:

		divisor = 1;

		DEV_ERR("%s: invalid hsclk_sel value = %lu",

				__func__, hsclk_sel);

		break;

	}

	return divisor;

}

static unsigned long hdmi_8996_vco_get_rate(struct clk *c)

{

	unsigned long freq = 0;

	unsigned long freq = 0, hsclk_sel = 0, tx_band = 0, dec_start = 0,

		      div_frac_start = 0, vco_clock_freq = 0;

	struct hdmi_pll_vco_clk *vco = to_hdmi_8996_vco_clk(c);

	struct mdss_pll_resources *io = vco->priv;

	if (mdss_pll_resource_enable(io, true)) {

		DEV_ERR("%s: pll resource can't be enabled\n", __func__);

		return freq;

	}

	dec_start = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_DEC_START_MODE0);

	div_frac_start =

		MDSS_PLL_REG_R(io->pll_base,

				QSERDES_COM_DIV_FRAC_START1_MODE0) |

		MDSS_PLL_REG_R(io->pll_base,

				QSERDES_COM_DIV_FRAC_START2_MODE0) << 8 |

		MDSS_PLL_REG_R(io->pll_base,

				QSERDES_COM_DIV_FRAC_START3_MODE0) << 16;

	vco_clock_freq = (dec_start + (div_frac_start / (1 << 20)))

		* 4 * (HDMI_REF_CLOCK);

	hsclk_sel = MDSS_PLL_REG_R(io->pll_base, QSERDES_COM_HSCLK_SEL) & 0x15;

	hsclk_sel = hdmi_get_hsclk_sel_divisor(hsclk_sel);

	tx_band = MDSS_PLL_REG_R(io->pll_base + HDMI_TX_L0_BASE_OFFSET,

			QSERDES_TX_L0_TX_BAND) & 0x3;

	freq = vco_clock_freq / (10 * hsclk_sel * (1 << tx_band));

	mdss_pll_resource_enable(io, false);

	DEV_DBG("%s: freq = %lu\n", __func__, freq);

	return freq;

}

config MSM_SDE_ROTATOR

	bool "QTI V4L2 based SDE Rotator"

	depends on ARCH_MSM && VIDEO_V4L2

	select V4L2_MEM2MEM_DEV

	select VIDEOBUF2_CORE

	select SW_SYNC if SYNC

	---help---

	  Enable support of V4L2 rotator driver.

 No newline at end of file