Merge "clk: qcom: Add additional clock debugfs support" into msm-4.8 (5bc4406a) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/clk/qcom/clk-alpha-pll.c

+74 −0

Original line number	Diff line number	Diff line
		@@ -414,6 +414,41 @@ static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
		return clamp(rate, min_freq, max_freq);
		}

		static void clk_alpha_pll_list_registers(struct seq_file f, struct clk_hw hw)
		{
		struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
		int size, i, val;

		static struct clk_register_data data[] = {
		{"PLL_MODE", 0x0},
		{"PLL_L_VAL", 0x4},
		{"PLL_ALPHA_VAL", 0x8},
		{"PLL_ALPHA_VAL_U", 0xC},
		{"PLL_USER_CTL", 0x10},
		{"PLL_CONFIG_CTL", 0x18},
		};

		static struct clk_register_data data1[] = {
		{"APSS_PLL_VOTE", 0x0},
		};

		size = ARRAY_SIZE(data);

		for (i = 0; i < size; i++) {
		regmap_read(pll->clkr.regmap, pll->offset + data[i].offset,
		&val);
		seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val);
		}

		regmap_read(pll->clkr.regmap, pll->offset + data[0].offset, &val);

		if (val & PLL_FSM_ENA) {
		regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +
		data1[0].offset, &val);
		seq_printf(f, "%20s: 0x%.8x\n", data1[0].name, val);
		}
		}

		void clk_fabia_pll_configure(struct clk_alpha_pll pll, struct regmap regmap,
		const struct pll_config *config)
		{
		@@ -617,12 +652,48 @@ static int clk_fabia_pll_set_rate(struct clk_hw *hw, unsigned long rate,
		return 0;
		}

		static void clk_fabia_pll_list_registers(struct seq_file f, struct clk_hw hw)
		{
		struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
		int size, i, val;

		static struct clk_register_data data[] = {
		{"PLL_MODE", 0x0},
		{"PLL_L_VAL", 0x4},
		{"PLL_FRAC_VAL", 0x38},
		{"PLL_USER_CTL", 0xc},
		{"PLL_CONFIG_CTL", 0x14},
		{"PLL_OPMODE", 0x2c},
		};

		static struct clk_register_data data1[] = {
		{"APSS_PLL_VOTE", 0x0},
		};

		size = ARRAY_SIZE(data);

		for (i = 0; i < size; i++) {
		regmap_read(pll->clkr.regmap, pll->offset + data[i].offset,
		&val);
		seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val);
		}

		regmap_read(pll->clkr.regmap, pll->offset + data[0].offset, &val);

		if (val & PLL_FSM_ENA) {
		regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +
		data1[0].offset, &val);
		seq_printf(f, "%20s: 0x%.8x\n", data1[0].name, val);
		}
		}

		const struct clk_ops clk_alpha_pll_ops = {
		.enable = clk_alpha_pll_enable,
		.disable = clk_alpha_pll_disable,
		.recalc_rate = clk_alpha_pll_recalc_rate,
		.round_rate = clk_alpha_pll_round_rate,
		.set_rate = clk_alpha_pll_set_rate,
		.list_registers = clk_alpha_pll_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);

		@@ -632,6 +703,7 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = {
		.recalc_rate = clk_alpha_pll_recalc_rate,
		.round_rate = clk_alpha_pll_round_rate,
		.set_rate = clk_alpha_pll_set_rate,
		.list_registers = clk_alpha_pll_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);

		@@ -641,6 +713,7 @@ const struct clk_ops clk_fabia_pll_ops = {
		.recalc_rate = clk_fabia_pll_recalc_rate,
		.round_rate = clk_alpha_pll_round_rate,
		.set_rate = clk_fabia_pll_set_rate,
		.list_registers = clk_fabia_pll_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_fabia_pll_ops);

		@@ -649,6 +722,7 @@ const struct clk_ops clk_fabia_fixed_pll_ops = {
		.disable = clk_fabia_pll_disable,
		.recalc_rate = clk_fabia_pll_recalc_rate,
		.round_rate = clk_alpha_pll_round_rate,
		.list_registers = clk_fabia_pll_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_fabia_fixed_pll_ops);

drivers/clk/qcom/clk-branch.c

+59 −0

Original line number	Diff line number	Diff line
		@@ -16,11 +16,13 @@
		#include <linux/err.h>
		#include <linux/delay.h>
		#include <linux/export.h>
		#include <linux/clk.h>
		#include <linux/clk-provider.h>
		#include <linux/regmap.h>
		#include <linux/clk/qcom.h>

		#include "clk-branch.h"
		#include "clk-regmap.h"

		static bool clk_branch_in_hwcg_mode(const struct clk_branch *br)
		{
		@@ -182,6 +184,43 @@ const struct clk_ops clk_branch_ops = {
		};
		EXPORT_SYMBOL_GPL(clk_branch_ops);

		static void clk_branch2_list_registers(struct seq_file f, struct clk_hw hw)
		{
		struct clk_branch *br = to_clk_branch(hw);
		struct clk_regmap *rclk = to_clk_regmap(hw);
		int size, i, val;

		static struct clk_register_data data[] = {
		{"CBCR", 0x0},
		};

		static struct clk_register_data data1[] = {
		{"APSS_VOTE", 0x0},
		{"APSS_SLEEP_VOTE", 0x4},
		};

		size = ARRAY_SIZE(data);

		for (i = 0; i < size; i++) {
		regmap_read(br->clkr.regmap, br->halt_reg + data[i].offset,
		&val);
		seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val);
		}

		if ((br->halt_check & BRANCH_HALT_VOTED) &&
		!(br->halt_check & BRANCH_VOTED)) {
		if (rclk->enable_reg) {
		size = ARRAY_SIZE(data1);
		for (i = 0; i < size; i++) {
		regmap_read(br->clkr.regmap, rclk->enable_reg +
		data1[i].offset, &val);
		seq_printf(f, "%20s: 0x%.8x\n",
		data1[i].name, val);
		}
		}
		}
		}

		static int clk_branch2_enable(struct clk_hw *hw)
		{
		return clk_branch_toggle(hw, true, clk_branch2_check_halt);
		@@ -197,6 +236,7 @@ const struct clk_ops clk_branch2_ops = {
		.disable = clk_branch2_disable,
		.is_enabled = clk_is_enabled_regmap,
		.set_flags = clk_branch_set_flags,
		.list_registers = clk_branch2_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_branch2_ops);

		@@ -229,10 +269,29 @@ static void clk_gate2_disable(struct clk_hw *hw)
		clk_gate_toggle(hw, false);
		}

		static void clk_gate2_list_registers(struct seq_file f, struct clk_hw hw)
		{
		struct clk_gate2 *gt = to_clk_gate2(hw);
		int size, i, val;

		static struct clk_register_data data[] = {
		{"EN_REG", 0x0},
		};

		size = ARRAY_SIZE(data);

		for (i = 0; i < size; i++) {
		regmap_read(gt->clkr.regmap, gt->clkr.enable_reg +
		data[i].offset, &val);
		seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val);
		}
		}

		const struct clk_ops clk_gate2_ops = {
		.enable = clk_gate2_enable,
		.disable = clk_gate2_disable,
		.is_enabled = clk_is_enabled_regmap,
		.list_registers = clk_gate2_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_gate2_ops);

drivers/clk/qcom/clk-rcg2.c

+54 −0

Original line number	Diff line number	Diff line
		@@ -310,6 +310,53 @@ static int clk_rcg2_configure(struct clk_rcg2 rcg, const struct freq_tbl f)
		return update_config(rcg);
		}

		static void clk_rcg2_list_registers(struct seq_file f, struct clk_hw hw)
		{
		struct clk_rcg2 *rcg = to_clk_rcg2(hw);
		int i = 0, size = 0, val;

		static struct clk_register_data data[] = {
		{"CMD_RCGR", 0x0},
		{"CFG_RCGR", 0x4},
		};

		static struct clk_register_data data1[] = {
		{"CMD_RCGR", 0x0},
		{"CFG_RCGR", 0x4},
		{"M_VAL", 0x8},
		{"N_VAL", 0xC},
		{"D_VAL", 0x10},
		};

		if (rcg->mnd_width) {
		size = ARRAY_SIZE(data1);
		for (i = 0; i < size; i++) {
		regmap_read(rcg->clkr.regmap, (rcg->cmd_rcgr +
		data1[i].offset), &val);
		seq_printf(f, "%20s: 0x%.8x\n", data1[i].name, val);
		}
		} else {
		size = ARRAY_SIZE(data);
		for (i = 0; i < size; i++) {
		regmap_read(rcg->clkr.regmap, (rcg->cmd_rcgr +
		data[i].offset), &val);
		seq_printf(f, "%20s: 0x%.8x\n", data[i].name, val);
		}
		}
		}

		/* Return the nth supported frequency for a given clock. */
		static long clk_rcg2_list_rate(struct clk_hw *hw, unsigned int n,
		unsigned long fmax)
		{
		struct clk_rcg2 *rcg = to_clk_rcg2(hw);

		if (!rcg->freq_tbl)
		return -ENXIO;

		return (rcg->freq_tbl + n)->freq;
		}

		static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
		{
		struct clk_rcg2 *rcg = to_clk_rcg2(hw);
		@@ -408,6 +455,8 @@ const struct clk_ops clk_rcg2_ops = {
		.determine_rate = clk_rcg2_determine_rate,
		.set_rate = clk_rcg2_set_rate,
		.set_rate_and_parent = clk_rcg2_set_rate_and_parent,
		.list_rate = clk_rcg2_list_rate,
		.list_registers = clk_rcg2_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_rcg2_ops);

		@@ -614,6 +663,7 @@ const struct clk_ops clk_edp_pixel_ops = {
		.set_rate = clk_edp_pixel_set_rate,
		.set_rate_and_parent = clk_edp_pixel_set_rate_and_parent,
		.determine_rate = clk_edp_pixel_determine_rate,
		.list_registers = clk_rcg2_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);

		@@ -672,6 +722,7 @@ const struct clk_ops clk_byte_ops = {
		.set_rate = clk_byte_set_rate,
		.set_rate_and_parent = clk_byte_set_rate_and_parent,
		.determine_rate = clk_byte_determine_rate,
		.list_registers = clk_rcg2_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_byte_ops);

		@@ -742,6 +793,7 @@ const struct clk_ops clk_byte2_ops = {
		.set_rate = clk_byte2_set_rate,
		.set_rate_and_parent = clk_byte2_set_rate_and_parent,
		.determine_rate = clk_byte2_determine_rate,
		.list_registers = clk_rcg2_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_byte2_ops);

		@@ -832,6 +884,7 @@ const struct clk_ops clk_pixel_ops = {
		.set_rate = clk_pixel_set_rate,
		.set_rate_and_parent = clk_pixel_set_rate_and_parent,
		.determine_rate = clk_pixel_determine_rate,
		.list_registers = clk_rcg2_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_pixel_ops);

		@@ -919,5 +972,6 @@ const struct clk_ops clk_gfx3d_ops = {
		.set_rate = clk_gfx3d_set_rate,
		.set_rate_and_parent = clk_gfx3d_set_rate_and_parent,
		.determine_rate = clk_gfx3d_determine_rate,
		.list_registers = clk_rcg2_list_registers,
		};
		EXPORT_SYMBOL_GPL(clk_gfx3d_ops);

drivers/clk/qcom/clk-regmap.h

+7 −1

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2014, The Linux Foundation. All rights reserved.
		* Copyright (c) 2014, 2016, The Linux Foundation. All rights reserved.
		*
		* This software is licensed under the terms of the GNU General Public
		* License version 2, as published by the Free Software Foundation, and
		@@ -15,6 +15,7 @@
		#define __QCOM_CLK_REGMAP_H__

		#include <linux/clk-provider.h>
		#include <linux/debugfs.h>

		struct regmap;

		@@ -41,4 +42,9 @@ int clk_enable_regmap(struct clk_hw *hw);
		void clk_disable_regmap(struct clk_hw *hw);
		int devm_clk_register_regmap(struct device dev, struct clk_regmap rclk);

		struct clk_register_data {
		char *name;
		u32 offset;
		};

		#endif