x86: mce: Remove old i386 machine check code (5bb38adc) · Commits · e / devices / android_kernel_fairphone_FP3

Documentation/feature-removal-schedule.txt

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		@@ -444,13 +444,3 @@ What: CONFIG_RFKILL_INPUT
		When: 2.6.33
		Why: Should be implemented in userspace, policy daemon.
		Who: Johannes Berg <johannes@sipsolutions.net>

		----------------------------

		What: CONFIG_X86_OLD_MCE
		When: 2.6.32
		Why: Remove the old legacy 32bit machine check code. This has been
		superseded by the newer machine check code from the 64bit port,
		but the old version has been kept around for easier testing. Note this
		doesn't impact the old P5 and WinChip machine check handlers.
		Who: Andi Kleen <andi@firstfloor.org>

arch/x86/Kconfig

+2 −33

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		@@ -781,21 +781,10 @@ config X86_MCE
		The action the kernel takes depends on the severity of the problem,
		ranging from warning messages to halting the machine.

		config X86_OLD_MCE
		depends on X86_32 && X86_MCE
		bool "Use legacy machine check code (will go away)"
		default n
		select X86_ANCIENT_MCE
		---help---
		Use the old i386 machine check code. This is merely intended for
		testing in a transition period. Try this if you run into any machine
		check related software problems, but report the problem to
		linux-kernel. When in doubt say no.

		config X86_NEW_MCE
		depends on X86_MCE
		bool
		default y if (!X86_OLD_MCE && X86_32) \|\| X86_64
		default y

		config X86_MCE_INTEL
		def_bool y
		@@ -835,29 +824,9 @@ config X86_MCE_INJECT
		If you don't know what a machine check is and you don't do kernel
		QA it is safe to say n.

		config X86_MCE_NONFATAL
		tristate "Check for non-fatal errors on AMD Athlon/Duron / Intel Pentium 4"
		depends on X86_OLD_MCE
		---help---
		Enabling this feature starts a timer that triggers every 5 seconds which
		will look at the machine check registers to see if anything happened.
		Non-fatal problems automatically get corrected (but still logged).
		Disable this if you don't want to see these messages.
		Seeing the messages this option prints out may be indicative of dying
		or out-of-spec (ie, overclocked) hardware.
		This option only does something on certain CPUs.
		(AMD Athlon/Duron and Intel Pentium 4)

		config X86_MCE_P4THERMAL
		bool "check for P4 thermal throttling interrupt."
		depends on X86_OLD_MCE && X86_MCE && (X86_UP_APIC \|\| SMP)
		---help---
		Enabling this feature will cause a message to be printed when the P4
		enters thermal throttling.

		config X86_THERMAL_VECTOR
		def_bool y
		depends on X86_MCE_P4THERMAL \|\| X86_MCE_INTEL
		depends on X86_MCE_INTEL

		config VM86
		bool "Enable VM86 support" if EMBEDDED

arch/x86/include/asm/mce.h

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		@@ -115,13 +115,6 @@ void mcheck_init(struct cpuinfo_x86 *c);
		static inline void mcheck_init(struct cpuinfo_x86 *c) {}
		#endif

		#ifdef CONFIG_X86_OLD_MCE
		extern int nr_mce_banks;
		void amd_mcheck_init(struct cpuinfo_x86 *c);
		void intel_p4_mcheck_init(struct cpuinfo_x86 *c);
		void intel_p6_mcheck_init(struct cpuinfo_x86 *c);
		#endif

		#ifdef CONFIG_X86_ANCIENT_MCE
		void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
		void winchip_mcheck_init(struct cpuinfo_x86 *c);
		@@ -208,11 +201,7 @@ extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);

		void intel_init_thermal(struct cpuinfo_x86 *c);

		#ifdef CONFIG_X86_NEW_MCE
		void mce_log_therm_throt_event(__u64 status);
		#else
		static inline void mce_log_therm_throt_event(__u64 status) {}
		#endif

		#endif /* __KERNEL__ */
		#endif /* _ASM_X86_MCE_H */

arch/x86/kernel/cpu/mcheck/Makefile

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		obj-y = mce.o

		obj-$(CONFIG_X86_NEW_MCE) += mce-severity.o
		obj-$(CONFIG_X86_OLD_MCE) += k7.o p4.o p6.o
		obj-$(CONFIG_X86_ANCIENT_MCE) += winchip.o p5.o
		obj-$(CONFIG_X86_MCE_INTEL) += mce_intel.o
		obj-$(CONFIG_X86_MCE_AMD) += mce_amd.o
		obj-$(CONFIG_X86_MCE_NONFATAL) += non-fatal.o
		obj-$(CONFIG_X86_MCE_THRESHOLD) += threshold.o
		obj-$(CONFIG_X86_MCE_INJECT) += mce-inject.o

arch/x86/kernel/cpu/mcheck/k7.c

deleted100644 → 0

+0 −116

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		/*
		* Athlon specific Machine Check Exception Reporting
		* (C) Copyright 2002 Dave Jones <davej@redhat.com>
		*/
		#include <linux/interrupt.h>
		#include <linux/kernel.h>
		#include <linux/types.h>
		#include <linux/init.h>
		#include <linux/smp.h>

		#include <asm/processor.h>
		#include <asm/system.h>
		#include <asm/mce.h>
		#include <asm/msr.h>

		/* Machine Check Handler For AMD Athlon/Duron: */
		static void k7_machine_check(struct pt_regs *regs, long error_code)
		{
		u32 alow, ahigh, high, low;
		u32 mcgstl, mcgsth;
		int recover = 1;
		int i;

		rdmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
		if (mcgstl & (1<<0)) /* Recoverable ? */
		recover = 0;

		printk(KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
		smp_processor_id(), mcgsth, mcgstl);

		for (i = 1; i < nr_mce_banks; i++) {
		rdmsr(MSR_IA32_MC0_STATUS+i*4, low, high);
		if (high & (1<<31)) {
		char misc[20];
		char addr[24];

		misc[0] = '\0';
		addr[0] = '\0';

		if (high & (1<<29))
		recover \|= 1;
		if (high & (1<<25))
		recover \|= 2;
		high &= ~(1<<31);

		if (high & (1<<27)) {
		rdmsr(MSR_IA32_MC0_MISC+i*4, alow, ahigh);
		snprintf(misc, 20, "[%08x%08x]", ahigh, alow);
		}
		if (high & (1<<26)) {
		rdmsr(MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
		snprintf(addr, 24, " at %08x%08x", ahigh, alow);
		}

		printk(KERN_EMERG "CPU %d: Bank %d: %08x%08x%s%s\n",
		smp_processor_id(), i, high, low, misc, addr);

		/* Clear it: */
		wrmsr(MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
		/* Serialize: */
		wmb();
		add_taint(TAINT_MACHINE_CHECK);
		}
		}

		if (recover & 2)
		panic("CPU context corrupt");
		if (recover & 1)
		panic("Unable to continue");

		printk(KERN_EMERG "Attempting to continue.\n");

		mcgstl &= ~(1<<2);
		wrmsr(MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
		}


		/* AMD K7 machine check is Intel like: */
		void amd_mcheck_init(struct cpuinfo_x86 *c)
		{
		u32 l, h;
		int i;

		if (!cpu_has(c, X86_FEATURE_MCE))
		return;

		machine_check_vector = k7_machine_check;
		/* Make sure the vector pointer is visible before we enable MCEs: */
		wmb();

		printk(KERN_INFO "Intel machine check architecture supported.\n");

		rdmsr(MSR_IA32_MCG_CAP, l, h);
		if (l & (1<<8)) /* Control register present ? */
		wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
		nr_mce_banks = l & 0xff;

		/*
		* Clear status for MC index 0 separately, we don't touch CTL,
		* as some K7 Athlons cause spurious MCEs when its enabled:
		*/
		if (boot_cpu_data.x86 == 6) {
		wrmsr(MSR_IA32_MC0_STATUS, 0x0, 0x0);
		i = 1;
		} else
		i = 0;

		for (; i < nr_mce_banks; i++) {
		wrmsr(MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
		wrmsr(MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
		}

		set_in_cr4(X86_CR4_MCE);
		printk(KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
		smp_processor_id());
		}