drm/i915: wire up CRC interrupt for ilk/snb (5b3a856b) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/gpu/drm/i915/i915_debugfs.c

+57 −17

Original line number	Original line	Diff line number	Diff line
	@@ -1914,6 +1914,7 @@ static const char * const pipe_crc_sources[] = {
	"plane1",		"plane1",
	"plane2",		"plane2",
	"pf",		"pf",
			"pipe",
	};		};

	static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)		static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
	@@ -1942,14 +1943,61 @@ static int display_crc_ctl_open(struct inode inode, struct file file)
	return single_open(file, display_crc_ctl_show, dev);		return single_open(file, display_crc_ctl_show, dev);
	}		}

			static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source source,
			uint32_t *val)
			{
			switch (source) {
			case INTEL_PIPE_CRC_SOURCE_PLANE1:
			*val = PIPE_CRC_ENABLE \| PIPE_CRC_SOURCE_PRIMARY_ILK;
			break;
			case INTEL_PIPE_CRC_SOURCE_PLANE2:
			*val = PIPE_CRC_ENABLE \| PIPE_CRC_SOURCE_SPRITE_ILK;
			break;
			case INTEL_PIPE_CRC_SOURCE_PF:
			return -EINVAL;
			case INTEL_PIPE_CRC_SOURCE_PIPE:
			*val = PIPE_CRC_ENABLE \| PIPE_CRC_SOURCE_PIPE_ILK;
			break;
			default:
			*val = 0;
			break;
			}

			return 0;
			}

			static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source source,
			uint32_t *val)
			{
			switch (source) {
			case INTEL_PIPE_CRC_SOURCE_PLANE1:
			*val = PIPE_CRC_ENABLE \| PIPE_CRC_SOURCE_PRIMARY_IVB;
			break;
			case INTEL_PIPE_CRC_SOURCE_PLANE2:
			*val = PIPE_CRC_ENABLE \| PIPE_CRC_SOURCE_SPRITE_IVB;
			break;
			case INTEL_PIPE_CRC_SOURCE_PF:
			*val = PIPE_CRC_ENABLE \| PIPE_CRC_SOURCE_PF_IVB;
			break;
			case INTEL_PIPE_CRC_SOURCE_PIPE:
			return -EINVAL;
			default:
			*val = 0;
			break;
			}

			return 0;
			}

	static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,		static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
	enum intel_pipe_crc_source source)		enum intel_pipe_crc_source source)
	{		{
	struct drm_i915_private *dev_priv = dev->dev_private;		struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];		struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
	u32 val;		u32 val;
			int ret;

	if (!IS_IVYBRIDGE(dev))		if (!(IS_IVYBRIDGE(dev) \|\| IS_GEN5(dev) \|\| IS_GEN6(dev)))
	return -ENODEV;		return -ENODEV;

	if (pipe_crc->source == source)		if (pipe_crc->source == source)
	@@ -1959,6 +2007,14 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
	if (pipe_crc->source && source)		if (pipe_crc->source && source)
	return -EINVAL;		return -EINVAL;

			if (IS_GEN5(dev) \|\| IS_GEN6(dev))
			ret = ilk_pipe_crc_ctl_reg(source, &val);
			else
			ret = ivb_pipe_crc_ctl_reg(source, &val);

			if (ret != 0)
			return ret;

	/* none -> real source transition */		/* none -> real source transition */
	if (source) {		if (source) {
	DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",		DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
	@@ -1976,22 +2032,6 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,

	pipe_crc->source = source;		pipe_crc->source = source;

	switch (source) {
	case INTEL_PIPE_CRC_SOURCE_PLANE1:
	val = PIPE_CRC_ENABLE \| PIPE_CRC_SOURCE_PRIMARY_IVB;
	break;
	case INTEL_PIPE_CRC_SOURCE_PLANE2:
	val = PIPE_CRC_ENABLE \| PIPE_CRC_SOURCE_SPRITE_IVB;
	break;
	case INTEL_PIPE_CRC_SOURCE_PF:
	val = PIPE_CRC_ENABLE \| PIPE_CRC_SOURCE_PF_IVB;
	break;
	case INTEL_PIPE_CRC_SOURCE_NONE:
	default:
	val = 0;
	break;
	}

	I915_WRITE(PIPE_CRC_CTL(pipe), val);		I915_WRITE(PIPE_CRC_CTL(pipe), val);
	POSTING_READ(PIPE_CRC_CTL(pipe));		POSTING_READ(PIPE_CRC_CTL(pipe));

drivers/gpu/drm/i915/i915_drv.h

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -1223,6 +1223,7 @@ enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_PLANE1,		INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,		INTEL_PIPE_CRC_SOURCE_PLANE2,
	INTEL_PIPE_CRC_SOURCE_PF,		INTEL_PIPE_CRC_SOURCE_PF,
			INTEL_PIPE_CRC_SOURCE_PIPE,
	INTEL_PIPE_CRC_SOURCE_MAX,		INTEL_PIPE_CRC_SOURCE_MAX,
	};		};

drivers/gpu/drm/i915/i915_irq.c

+24 −2

Original line number	Original line	Diff line number	Diff line
	@@ -1240,8 +1240,22 @@ static void ivb_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
	I915_READ(PIPE_CRC_RES_5_IVB(pipe)),		I915_READ(PIPE_CRC_RES_5_IVB(pipe)),
	I915_READ(PIPEFRAME(pipe)));		I915_READ(PIPEFRAME(pipe)));
	}		}

			static void ilk_pipe_crc_update(struct drm_device *dev, enum pipe pipe)
			{
			struct drm_i915_private *dev_priv = dev->dev_private;

			display_pipe_crc_update(dev, pipe,
			I915_READ(PIPE_CRC_RES_RED_ILK(pipe)),
			I915_READ(PIPE_CRC_RES_GREEN_ILK(pipe)),
			I915_READ(PIPE_CRC_RES_BLUE_ILK(pipe)),
			I915_READ(PIPE_CRC_RES_RES1_ILK(pipe)),
			I915_READ(PIPE_CRC_RES_RES2_ILK(pipe)),
			I915_READ(PIPEFRAME(pipe)));
			}
	#else		#else
	static inline void ivb_pipe_crc_update(struct drm_device *dev, int pipe) {}		static inline void ivb_pipe_crc_update(struct drm_device *dev, int pipe) {}
			static inline void ilk_pipe_crc_update(struct drm_device *dev, int pipe) {}
	#endif		#endif

	/* The RPS events need forcewake, so we add them to a work queue and mask their		/* The RPS events need forcewake, so we add them to a work queue and mask their
	@@ -1524,6 +1538,12 @@ static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
	if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))		if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
	DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");		DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");

			if (de_iir & DE_PIPEA_CRC_DONE)
			ilk_pipe_crc_update(dev, PIPE_A);

			if (de_iir & DE_PIPEB_CRC_DONE)
			ilk_pipe_crc_update(dev, PIPE_B);

	if (de_iir & DE_PLANEA_FLIP_DONE) {		if (de_iir & DE_PLANEA_FLIP_DONE) {
	intel_prepare_page_flip(dev, 0);		intel_prepare_page_flip(dev, 0);
	intel_finish_page_flip_plane(dev, 0);		intel_finish_page_flip_plane(dev, 0);
	@@ -2500,8 +2520,10 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
	} else {		} else {
	display_mask = (DE_MASTER_IRQ_CONTROL \| DE_GSE \| DE_PCH_EVENT \|		display_mask = (DE_MASTER_IRQ_CONTROL \| DE_GSE \| DE_PCH_EVENT \|
	DE_PLANEA_FLIP_DONE \| DE_PLANEB_FLIP_DONE \|		DE_PLANEA_FLIP_DONE \| DE_PLANEB_FLIP_DONE \|
	DE_AUX_CHANNEL_A \| DE_PIPEB_FIFO_UNDERRUN \|		DE_AUX_CHANNEL_A \|
	DE_PIPEA_FIFO_UNDERRUN \| DE_POISON);		DE_PIPEB_FIFO_UNDERRUN \| DE_PIPEA_FIFO_UNDERRUN \|
			DE_PIPEB_CRC_DONE \| DE_PIPEA_CRC_DONE \|
			DE_POISON);
	extra_mask = DE_PIPEA_VBLANK \| DE_PIPEB_VBLANK \| DE_PCU_EVENT;		extra_mask = DE_PIPEA_VBLANK \| DE_PIPEB_VBLANK \| DE_PCU_EVENT;
	}		}

drivers/gpu/drm/i915/i915_reg.h

+2 −0

Original line number	Original line	Diff line number	Diff line
	@@ -3918,12 +3918,14 @@
	#define DE_PIPEB_ODD_FIELD (1 << 13)		#define DE_PIPEB_ODD_FIELD (1 << 13)
	#define DE_PIPEB_LINE_COMPARE (1 << 12)		#define DE_PIPEB_LINE_COMPARE (1 << 12)
	#define DE_PIPEB_VSYNC (1 << 11)		#define DE_PIPEB_VSYNC (1 << 11)
			#define DE_PIPEB_CRC_DONE (1 << 10)
	#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)		#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
	#define DE_PIPEA_VBLANK (1 << 7)		#define DE_PIPEA_VBLANK (1 << 7)
	#define DE_PIPEA_EVEN_FIELD (1 << 6)		#define DE_PIPEA_EVEN_FIELD (1 << 6)
	#define DE_PIPEA_ODD_FIELD (1 << 5)		#define DE_PIPEA_ODD_FIELD (1 << 5)
	#define DE_PIPEA_LINE_COMPARE (1 << 4)		#define DE_PIPEA_LINE_COMPARE (1 << 4)
	#define DE_PIPEA_VSYNC (1 << 3)		#define DE_PIPEA_VSYNC (1 << 3)
			#define DE_PIPEA_CRC_DONE (1 << 2)
	#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)		#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)

	/* More Ivybridge lolz */		/* More Ivybridge lolz */