Merge branch 'i2c-for-ben' of... (5a93f420) · Commits · e / devices / android_kernel_fairphone_FP3

arch/arm/mach-omap2/clock24xx.h

+2 −2

Original line number	Diff line number	Diff line
		@@ -2321,7 +2321,7 @@ static struct clk i2c2_fck = {
		};

		static struct clk i2chs2_fck = {
		.name = "i2chs_fck",
		.name = "i2c_fck",
		.id = 2,
		.parent = &func_96m_ck,
		.flags = CLOCK_IN_OMAP243X,
		@@ -2354,7 +2354,7 @@ static struct clk i2c1_fck = {
		};

		static struct clk i2chs1_fck = {
		.name = "i2chs_fck",
		.name = "i2c_fck",
		.id = 1,
		.parent = &func_96m_ck,
		.flags = CLOCK_IN_OMAP243X,

drivers/i2c/busses/i2c-omap.c

+328 −92

Original line number	Diff line number	Diff line
		@@ -2,13 +2,16 @@
		* TI OMAP I2C master mode driver
		*
		* Copyright (C) 2003 MontaVista Software, Inc.
		* Copyright (C) 2004 Texas Instruments.
		*
		* Updated to work with multiple I2C interfaces on 24xx by
		* Tony Lindgren <tony@atomide.com> and Imre Deak <imre.deak@nokia.com>
		* Copyright (C) 2005 Nokia Corporation
		* Copyright (C) 2004 - 2007 Texas Instruments.
		*
		* Cleaned up by Juha Yrjölä <juha.yrjola@nokia.com>
		* Originally written by MontaVista Software, Inc.
		* Additional contributions by:
		* Tony Lindgren <tony@atomide.com>
		* Imre Deak <imre.deak@nokia.com>
		* Juha Yrjölä <juha.yrjola@solidboot.com>
		* Syed Khasim <x0khasim@ti.com>
		* Nishant Menon <nm@ti.com>
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License as published by
		@@ -33,8 +36,14 @@
		#include <linux/completion.h>
		#include <linux/platform_device.h>
		#include <linux/clk.h>
		#include <linux/io.h>

		/* I2C controller revisions */
		#define OMAP_I2C_REV_2 0x20

		#include <asm/io.h>
		/* I2C controller revisions present on specific hardware */
		#define OMAP_I2C_REV_ON_2430 0x36
		#define OMAP_I2C_REV_ON_3430 0x3C

		/* timeout waiting for the controller to respond */
		#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
		@@ -43,6 +52,8 @@
		#define OMAP_I2C_IE_REG 0x04
		#define OMAP_I2C_STAT_REG 0x08
		#define OMAP_I2C_IV_REG 0x0c
		/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
		#define OMAP_I2C_WE_REG 0x0c
		#define OMAP_I2C_SYSS_REG 0x10
		#define OMAP_I2C_BUF_REG 0x14
		#define OMAP_I2C_CNT_REG 0x18
		@@ -55,8 +66,11 @@
		#define OMAP_I2C_SCLL_REG 0x34
		#define OMAP_I2C_SCLH_REG 0x38
		#define OMAP_I2C_SYSTEST_REG 0x3c
		#define OMAP_I2C_BUFSTAT_REG 0x40

		/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
		#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
		#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
		#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
		#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
		#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
		@@ -64,7 +78,8 @@
		#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */

		/* I2C Status Register (OMAP_I2C_STAT): */
		#define OMAP_I2C_STAT_SBD (1 << 15) /* Single byte data */
		#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
		#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
		#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
		#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
		#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
		@@ -76,13 +91,34 @@
		#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
		#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */

		/* I2C WE wakeup enable register */
		#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
		#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
		#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
		#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
		#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
		#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
		#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
		#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
		#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
		#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */

		#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE \| OMAP_I2C_WE_RDR_WE \| \
		OMAP_I2C_WE_AAS_WE \| OMAP_I2C_WE_BF_WE \| \
		OMAP_I2C_WE_STC_WE \| OMAP_I2C_WE_GC_WE \| \
		OMAP_I2C_WE_DRDY_WE \| OMAP_I2C_WE_ARDY_WE \| \
		OMAP_I2C_WE_NACK_WE \| OMAP_I2C_WE_AL_WE)

		/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
		#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
		#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
		#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
		#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */

		/* I2C Configuration Register (OMAP_I2C_CON): */
		#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
		#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
		#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
		#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
		#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
		#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
		@@ -91,6 +127,10 @@
		#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
		#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */

		/* I2C SCL time value when Master */
		#define OMAP_I2C_SCLL_HSSCLL 8
		#define OMAP_I2C_SCLH_HSSCLH 8

		/* I2C System Test Register (OMAP_I2C_SYSTEST): */
		#ifdef DEBUG
		#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
		@@ -103,17 +143,19 @@
		#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
		#endif

		/* I2C System Status register (OMAP_I2C_SYSS): */
		#define OMAP_I2C_SYSS_RDONE (1 << 0) /* Reset Done */
		/* OCP_SYSSTATUS bit definitions */
		#define SYSS_RESETDONE_MASK (1 << 0)

		/* I2C System Configuration Register (OMAP_I2C_SYSC): */
		#define OMAP_I2C_SYSC_SRST (1 << 1) /* Soft Reset */
		/* OCP_SYSCONFIG bit definitions */
		#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
		#define SYSC_SIDLEMODE_MASK (0x3 << 3)
		#define SYSC_ENAWAKEUP_MASK (1 << 2)
		#define SYSC_SOFTRESET_MASK (1 << 1)
		#define SYSC_AUTOIDLE_MASK (1 << 0)

		#define SYSC_IDLEMODE_SMART 0x2
		#define SYSC_CLOCKACTIVITY_FCLK 0x2

		/* REVISIT: Use platform_data instead of module parameters */
		/* Fast Mode = 400 kHz, Standard = 100 kHz */
		static int clock = 100; /* Default: 100 kHz */
		module_param(clock, int, 0);
		MODULE_PARM_DESC(clock, "Set I2C clock in kHz: 400=fast mode (default == 100)");

		struct omap_i2c_dev {
		struct device *dev;
		@@ -123,11 +165,17 @@ struct omap_i2c_dev {
		struct clk fclk; / Functional clock */
		struct completion cmd_complete;
		struct resource *ioarea;
		u32 speed; /* Speed of bus in Khz */
		u16 cmd_err;
		u8 *buf;
		size_t buf_len;
		struct i2c_adapter adapter;
		unsigned rev1:1;
		u8 fifo_size; /* use as flag and value
		* fifo_size==0 implies no fifo
		* if set, should be trsh+1
		*/
		u8 rev;
		unsigned b_hw:1; /* bad h/w fixes */
		unsigned idle:1;
		u16 iestate; /* Saved interrupt register */
		};
		@@ -143,9 +191,9 @@ static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
		return __raw_readw(i2c_dev->base + reg);
		}

		static int omap_i2c_get_clocks(struct omap_i2c_dev *dev)
		static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
		{
		if (cpu_is_omap16xx() \|\| cpu_is_omap24xx()) {
		if (cpu_is_omap16xx() \|\| cpu_class_is_omap2()) {
		dev->iclk = clk_get(dev->dev, "i2c_ick");
		if (IS_ERR(dev->iclk)) {
		dev->iclk = NULL;
		@@ -178,25 +226,33 @@ static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)

		static void omap_i2c_unidle(struct omap_i2c_dev *dev)
		{
		WARN_ON(!dev->idle);

		if (dev->iclk != NULL)
		clk_enable(dev->iclk);
		clk_enable(dev->fclk);
		dev->idle = 0;
		if (dev->iestate)
		omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
		dev->idle = 0;
		}

		static void omap_i2c_idle(struct omap_i2c_dev *dev)
		{
		u16 iv;

		dev->idle = 1;
		WARN_ON(dev->idle);

		dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
		omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
		if (dev->rev1)
		if (dev->rev < OMAP_I2C_REV_2) {
		iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
		else
		} else {
		omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);

		/* Flush posted write before the dev->idle store occurs */
		omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
		}
		dev->idle = 1;
		clk_disable(dev->fclk);
		if (dev->iclk != NULL)
		clk_disable(dev->iclk);
		@@ -204,18 +260,20 @@ static void omap_i2c_idle(struct omap_i2c_dev *dev)

		static int omap_i2c_init(struct omap_i2c_dev *dev)
		{
		u16 psc = 0;
		u16 psc = 0, scll = 0, sclh = 0;
		u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
		unsigned long fclk_rate = 12000000;
		unsigned long timeout;
		unsigned long internal_clk = 0;

		if (!dev->rev1) {
		omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
		if (dev->rev >= OMAP_I2C_REV_2) {
		omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
		/* For some reason we need to set the EN bit before the
		* reset done bit gets set. */
		timeout = jiffies + OMAP_I2C_TIMEOUT;
		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
		while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
		OMAP_I2C_SYSS_RDONE)) {
		SYSS_RESETDONE_MASK)) {
		if (time_after(jiffies, timeout)) {
		dev_warn(dev->dev, "timeout waiting "
		"for controller reset\n");
		@@ -223,6 +281,33 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
		}
		msleep(1);
		}

		/* SYSC register is cleared by the reset; rewrite it */
		if (dev->rev == OMAP_I2C_REV_ON_2430) {

		omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
		SYSC_AUTOIDLE_MASK);

		} else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
		u32 v;

		v = SYSC_AUTOIDLE_MASK;
		v \|= SYSC_ENAWAKEUP_MASK;
		v \|= (SYSC_IDLEMODE_SMART <<
		__ffs(SYSC_SIDLEMODE_MASK));
		v \|= (SYSC_CLOCKACTIVITY_FCLK <<
		__ffs(SYSC_CLOCKACTIVITY_MASK));

		omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, v);
		/*
		* Enabling all wakup sources to stop I2C freezing on
		* WFI instruction.
		* REVISIT: Some wkup sources might not be needed.
		*/
		omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
		OMAP_I2C_WE_ALL);

		}
		}
		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);

		@@ -249,18 +334,55 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
		psc = fclk_rate / 12000000;
		}

		/* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
		omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
		if (cpu_is_omap2430() \|\| cpu_is_omap34xx()) {

		/* HSI2C controller internal clk rate should be 19.2 Mhz */
		internal_clk = 19200;
		fclk_rate = clk_get_rate(dev->fclk) / 1000;

		/* Compute prescaler divisor */
		psc = fclk_rate / internal_clk;
		psc = psc - 1;

		/* If configured for High Speed */
		if (dev->speed > 400) {
		/* For first phase of HS mode */
		fsscll = internal_clk / (400 * 2) - 6;
		fssclh = internal_clk / (400 * 2) - 6;

		/* For second phase of HS mode */
		hsscll = fclk_rate / (dev->speed * 2) - 6;
		hssclh = fclk_rate / (dev->speed * 2) - 6;
		} else {
		/* To handle F/S modes */
		fsscll = internal_clk / (dev->speed * 2) - 6;
		fssclh = internal_clk / (dev->speed * 2) - 6;
		}
		scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) \| fsscll;
		sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) \| fssclh;
		} else {
		/* Program desired operating rate */
		fclk_rate /= (psc + 1) * 1000;
		if (psc > 2)
		psc = 2;
		scll = fclk_rate / (dev->speed * 2) - 7 + psc;
		sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
		}

		/* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
		omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);

		omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG,
		fclk_rate / (clock * 2) - 7 + psc);
		omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG,
		fclk_rate / (clock * 2) - 7 + psc);
		/* SCL low and high time values */
		omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
		omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);

		if (dev->fifo_size)
		/* Note: setup required fifo size - 1 */
		omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
		(dev->fifo_size - 1) << 8 \| /* RTRSH */
		OMAP_I2C_BUF_RXFIF_CLR \|
		(dev->fifo_size - 1) \| /* XTRSH */
		OMAP_I2C_BUF_TXFIF_CLR);

		/* Take the I2C module out of reset: */
		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
		@@ -269,7 +391,8 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
		omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
		(OMAP_I2C_IE_XRDY \| OMAP_I2C_IE_RRDY \|
		OMAP_I2C_IE_ARDY \| OMAP_I2C_IE_NACK \|
		OMAP_I2C_IE_AL));
		OMAP_I2C_IE_AL) \| ((dev->fifo_size) ?
		(OMAP_I2C_IE_RDR \| OMAP_I2C_IE_XDR) : 0));
		return 0;
		}

		@@ -316,19 +439,58 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,

		omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);

		/* Clear the FIFO Buffers */
		w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
		w \|= OMAP_I2C_BUF_RXFIF_CLR \| OMAP_I2C_BUF_TXFIF_CLR;
		omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);

		init_completion(&dev->cmd_complete);
		dev->cmd_err = 0;

		w = OMAP_I2C_CON_EN \| OMAP_I2C_CON_MST \| OMAP_I2C_CON_STT;

		/* High speed configuration */
		if (dev->speed > 400)
		w \|= OMAP_I2C_CON_OPMODE_HS;

		if (msg->flags & I2C_M_TEN)
		w \|= OMAP_I2C_CON_XA;
		if (!(msg->flags & I2C_M_RD))
		w \|= OMAP_I2C_CON_TRX;
		if (stop)

		if (!dev->b_hw && stop)
		w \|= OMAP_I2C_CON_STP;

		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);

		/*
		* Don't write stt and stp together on some hardware.
		*/
		if (dev->b_hw && stop) {
		unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
		u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
		while (con & OMAP_I2C_CON_STT) {
		con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);

		/* Let the user know if i2c is in a bad state */
		if (time_after(jiffies, delay)) {
		dev_err(dev->dev, "controller timed out "
		"waiting for start condition to finish\n");
		return -ETIMEDOUT;
		}
		cpu_relax();
		}

		w \|= OMAP_I2C_CON_STP;
		w &= ~OMAP_I2C_CON_STT;
		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
		}

		r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
		/*
		* REVISIT: We should abort the transfer on signals, but the bus goes
		* into arbitration and we're currently unable to recover from it.
		*/
		r = wait_for_completion_timeout(&dev->cmd_complete,
		OMAP_I2C_TIMEOUT);
		dev->buf_len = 0;
		if (r < 0)
		@@ -376,7 +538,8 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)

		omap_i2c_unidle(dev);

		if ((r = omap_i2c_wait_for_bb(dev)) < 0)
		r = omap_i2c_wait_for_bb(dev);
		if (r < 0)
		goto out;

		for (i = 0; i < num; i++) {
		@@ -411,6 +574,9 @@ omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
		omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
		}

		/* rev1 devices are apparently only on some 15xx */
		#ifdef CONFIG_ARCH_OMAP15XX

		static irqreturn_t
		omap_i2c_rev1_isr(int this_irq, void *dev_id)
		{
		@@ -465,6 +631,9 @@ omap_i2c_rev1_isr(int this_irq, void *dev_id)

		return IRQ_HANDLED;
		}
		#else
		#define omap_i2c_rev1_isr NULL
		#endif

		static irqreturn_t
		omap_i2c_isr(int this_irq, void *dev_id)
		@@ -472,7 +641,7 @@ omap_i2c_isr(int this_irq, void *dev_id)
		struct omap_i2c_dev *dev = dev_id;
		u16 bits;
		u16 stat, w;
		int count = 0;
		int err, count = 0;

		if (dev->idle)
		return IRQ_NONE;
		@@ -487,39 +656,96 @@ omap_i2c_isr(int this_irq, void *dev_id)

		omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);

		if (stat & OMAP_I2C_STAT_ARDY) {
		omap_i2c_complete_cmd(dev, 0);
		continue;
		err = 0;
		if (stat & OMAP_I2C_STAT_NACK) {
		err \|= OMAP_I2C_STAT_NACK;
		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
		OMAP_I2C_CON_STP);
		}
		if (stat & OMAP_I2C_STAT_RRDY) {
		if (stat & OMAP_I2C_STAT_AL) {
		dev_err(dev->dev, "Arbitration lost\n");
		err \|= OMAP_I2C_STAT_AL;
		}
		if (stat & (OMAP_I2C_STAT_ARDY \| OMAP_I2C_STAT_NACK \|
		OMAP_I2C_STAT_AL))
		omap_i2c_complete_cmd(dev, err);
		if (stat & (OMAP_I2C_STAT_RRDY \| OMAP_I2C_STAT_RDR)) {
		u8 num_bytes = 1;
		if (dev->fifo_size) {
		if (stat & OMAP_I2C_STAT_RRDY)
		num_bytes = dev->fifo_size;
		else
		num_bytes = omap_i2c_read_reg(dev,
		OMAP_I2C_BUFSTAT_REG);
		}
		while (num_bytes) {
		num_bytes--;
		w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
		if (dev->buf_len) {
		*dev->buf++ = w;
		dev->buf_len--;
		/* Data reg from 2430 is 8 bit wide */
		if (!cpu_is_omap2430() &&
		!cpu_is_omap34xx()) {
		if (dev->buf_len) {
		*dev->buf++ = w >> 8;
		dev->buf_len--;
		}
		} else
		dev_err(dev->dev, "RRDY IRQ while no data "
		}
		} else {
		if (stat & OMAP_I2C_STAT_RRDY)
		dev_err(dev->dev,
		"RRDY IRQ while no data"
		" requested\n");
		omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
		if (stat & OMAP_I2C_STAT_RDR)
		dev_err(dev->dev,
		"RDR IRQ while no data"
		" requested\n");
		break;
		}
		}
		omap_i2c_ack_stat(dev,
		stat & (OMAP_I2C_STAT_RRDY \| OMAP_I2C_STAT_RDR));
		continue;
		}
		if (stat & OMAP_I2C_STAT_XRDY) {
		if (stat & (OMAP_I2C_STAT_XRDY \| OMAP_I2C_STAT_XDR)) {
		u8 num_bytes = 1;
		if (dev->fifo_size) {
		if (stat & OMAP_I2C_STAT_XRDY)
		num_bytes = dev->fifo_size;
		else
		num_bytes = omap_i2c_read_reg(dev,
		OMAP_I2C_BUFSTAT_REG);
		}
		while (num_bytes) {
		num_bytes--;
		w = 0;
		if (dev->buf_len) {
		w = *dev->buf++;
		dev->buf_len--;
		/* Data reg from 2430 is 8 bit wide */
		if (!cpu_is_omap2430() &&
		!cpu_is_omap34xx()) {
		if (dev->buf_len) {
		w \|= *dev->buf++ << 8;
		dev->buf_len--;
		}
		} else
		dev_err(dev->dev, "XRDY IRQ while no "
		}
		} else {
		if (stat & OMAP_I2C_STAT_XRDY)
		dev_err(dev->dev,
		"XRDY IRQ while no "
		"data to send\n");
		if (stat & OMAP_I2C_STAT_XDR)
		dev_err(dev->dev,
		"XDR IRQ while no "
		"data to send\n");
		break;
		}
		omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
		omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
		}
		omap_i2c_ack_stat(dev,
		stat & (OMAP_I2C_STAT_XRDY \| OMAP_I2C_STAT_XDR));
		continue;
		}
		if (stat & OMAP_I2C_STAT_ROVR) {
		@@ -527,18 +753,9 @@ omap_i2c_isr(int this_irq, void *dev_id)
		dev->cmd_err \|= OMAP_I2C_STAT_ROVR;
		}
		if (stat & OMAP_I2C_STAT_XUDF) {
		dev_err(dev->dev, "Transmit overflow\n");
		dev_err(dev->dev, "Transmit underflow\n");
		dev->cmd_err \|= OMAP_I2C_STAT_XUDF;
		}
		if (stat & OMAP_I2C_STAT_NACK) {
		omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
		omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
		OMAP_I2C_CON_STP);
		}
		if (stat & OMAP_I2C_STAT_AL) {
		dev_err(dev->dev, "Arbitration lost\n");
		omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
		}
		}

		return count ? IRQ_HANDLED : IRQ_NONE;
		@@ -549,13 +766,15 @@ static const struct i2c_algorithm omap_i2c_algo = {
		.functionality = omap_i2c_func,
		};

		static int
		static int __init
		omap_i2c_probe(struct platform_device *pdev)
		{
		struct omap_i2c_dev *dev;
		struct i2c_adapter *adap;
		struct resource mem, irq, *ioarea;
		void *isr;
		int r;
		u32 speed = 0;

		/* NOTE: driver uses the static register mapping */
		mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
		@@ -576,17 +795,19 @@ omap_i2c_probe(struct platform_device *pdev)
		return -EBUSY;
		}

		if (clock > 200)
		clock = 400; /* Fast mode */
		else
		clock = 100; /* Standard mode */

		dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
		if (!dev) {
		r = -ENOMEM;
		goto err_release_region;
		}

		if (pdev->dev.platform_data != NULL)
		speed = (u32 )pdev->dev.platform_data;
		else
		speed = 100; /* Defualt speed */

		dev->speed = speed;
		dev->idle = 1;
		dev->dev = &pdev->dev;
		dev->irq = irq->start;
		dev->base = ioremap(mem->start, mem->end - mem->start + 1);
		@@ -602,22 +823,39 @@ omap_i2c_probe(struct platform_device *pdev)

		omap_i2c_unidle(dev);

		if (cpu_is_omap15xx())
		dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20;
		dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;

		if (cpu_is_omap2430() \|\| cpu_is_omap34xx()) {
		u16 s;

		/* Set up the fifo size - Get total size */
		s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
		dev->fifo_size = 0x8 << s;

		/*
		* Set up notification threshold as half the total available
		* size. This is to ensure that we can handle the status on int
		* call back latencies.
		*/
		dev->fifo_size = (dev->fifo_size / 2);
		dev->b_hw = 1; /* Enable hardware fixes */
		}

		/* reset ASAP, clearing any IRQs */
		omap_i2c_init(dev);

		r = request_irq(dev->irq, dev->rev1 ? omap_i2c_rev1_isr : omap_i2c_isr,
		0, pdev->name, dev);
		isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr;
		r = request_irq(dev->irq, isr, 0, pdev->name, dev);

		if (r) {
		dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
		goto err_unuse_clocks;
		}
		r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;

		dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
		pdev->id, r >> 4, r & 0xf, clock);
		pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);

		omap_i2c_idle(dev);

		adap = &dev->adapter;
		i2c_set_adapdata(adap, dev);
		@@ -635,8 +873,6 @@ omap_i2c_probe(struct platform_device *pdev)
		goto err_free_irq;
		}

		omap_i2c_idle(dev);

		return 0;

		err_free_irq: