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Commit 59e21e3d authored by Borislav Petkov's avatar Borislav Petkov Committed by Ingo Molnar
Browse files

x86/cpufeature: Replace cpu_has_tsc with boot_cpu_has() usage 



Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Thomas Sailer <t.sailer@alumni.ethz.ch>
Link: http://lkml.kernel.org/r/1459801503-15600-7-git-send-email-bp@alien8.de


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent a402a8df

arch/x86/include/asm/cpufeature.h

+0 −1
Original line number Diff line number Diff line
@@ -118,7 +118,6 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; 
	set_bit(bit, (unsigned long *)cpu_caps_set);	\

} while (0)



#define cpu_has_tsc		boot_cpu_has(X86_FEATURE_TSC)

#define cpu_has_apic		boot_cpu_has(X86_FEATURE_APIC)

#define cpu_has_fxsr		boot_cpu_has(X86_FEATURE_FXSR)

#define cpu_has_xsave		boot_cpu_has(X86_FEATURE_XSAVE)

arch/x86/include/asm/tsc.h

+1 −1
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ extern void disable_TSC(void); 
static inline cycles_t get_cycles(void)

{

#ifndef CONFIG_X86_TSC

	if (!cpu_has_tsc)

	if (!boot_cpu_has(X86_FEATURE_TSC))

		return 0;

#endif

arch/x86/kernel/apic/apic.c

+5 −5
Original line number Diff line number Diff line
@@ -607,7 +607,7 @@ static void __init lapic_cal_handler(struct clock_event_device *dev) 
	long tapic = apic_read(APIC_TMCCT);

	unsigned long pm = acpi_pm_read_early();



	if (cpu_has_tsc)

	if (boot_cpu_has(X86_FEATURE_TSC))

		tsc = rdtsc();



	switch (lapic_cal_loops++) {
@@ -668,7 +668,7 @@ calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 
	*delta = (long)res;



	/* Correct the tsc counter value */

	if (cpu_has_tsc) {

	if (boot_cpu_has(X86_FEATURE_TSC)) {

		res = (((u64)(*deltatsc)) * pm_100ms);

		do_div(res, deltapm);

		apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
@@ -760,7 +760,7 @@ static int __init calibrate_APIC_clock(void) 
	apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",

		    lapic_timer_frequency);



	if (cpu_has_tsc) {

	if (boot_cpu_has(X86_FEATURE_TSC)) {

		apic_printk(APIC_VERBOSE, "..... CPU clock speed is "

			    "%ld.%04ld MHz.\n",

			    (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
@@ -1227,7 +1227,7 @@ void setup_local_APIC(void) 
	unsigned long long tsc = 0, ntsc;

	long long max_loops = cpu_khz ? cpu_khz : 1000000;



	if (cpu_has_tsc)

	if (boot_cpu_has(X86_FEATURE_TSC))

		tsc = rdtsc();



	if (disable_apic) {
@@ -1311,7 +1311,7 @@ void setup_local_APIC(void) 
			break;

		}

		if (queued) {

			if (cpu_has_tsc && cpu_khz) {

			if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {

				ntsc = rdtsc();

				max_loops = (cpu_khz << 10) - (ntsc - tsc);

			} else

arch/x86/kernel/cpu/common.c

+1 −1
Original line number Diff line number Diff line
@@ -1558,7 +1558,7 @@ void cpu_init(void) 
	pr_info("Initializing CPU#%d\n", cpu);



	if (cpu_feature_enabled(X86_FEATURE_VME) ||

	    cpu_has_tsc ||

	    boot_cpu_has(X86_FEATURE_TSC) ||

	    boot_cpu_has(X86_FEATURE_DE))

		cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);

arch/x86/kernel/tsc.c

+6 −6
Original line number Diff line number Diff line
@@ -36,7 +36,7 @@ static int __read_mostly tsc_unstable; 


/* native_sched_clock() is called before tsc_init(), so

   we must start with the TSC soft disabled to prevent

   erroneous rdtsc usage on !cpu_has_tsc processors */

   erroneous rdtsc usage on !boot_cpu_has(X86_FEATURE_TSC) processors */

static int __read_mostly tsc_disabled = -1;



static DEFINE_STATIC_KEY_FALSE(__use_tsc);
@@ -834,7 +834,7 @@ int recalibrate_cpu_khz(void) 
#ifndef CONFIG_SMP

	unsigned long cpu_khz_old = cpu_khz;



	if (cpu_has_tsc) {

	if (boot_cpu_has(X86_FEATURE_TSC)) {

		tsc_khz = x86_platform.calibrate_tsc();

		cpu_khz = tsc_khz;

		cpu_data(0).loops_per_jiffy =
@@ -956,7 +956,7 @@ static struct notifier_block time_cpufreq_notifier_block = { 


static int __init cpufreq_tsc(void)

{

	if (!cpu_has_tsc)

	if (!boot_cpu_has(X86_FEATURE_TSC))

		return 0;

	if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))

		return 0;
@@ -1081,7 +1081,7 @@ static void __init check_system_tsc_reliable(void) 
 */

int unsynchronized_tsc(void)

{

	if (!cpu_has_tsc || tsc_unstable)

	if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_unstable)

		return 1;



#ifdef CONFIG_SMP
@@ -1205,7 +1205,7 @@ static void tsc_refine_calibration_work(struct work_struct *work) 


static int __init init_tsc_clocksource(void)

{

	if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz)

	if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_disabled > 0 || !tsc_khz)

		return 0;



	if (tsc_clocksource_reliable)
@@ -1242,7 +1242,7 @@ void __init tsc_init(void) 
	u64 lpj;

	int cpu;



	if (!cpu_has_tsc) {

	if (!boot_cpu_has(X86_FEATURE_TSC)) {

		setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);

		return;

	}