Staging: Merge branch 'tidspbridge-for-2.6.39' of...

obj-$(CONFIG_TIDSPBRIDGE)	+= bridgedriver.o

libgen = gen/gb.o gen/gs.o gen/gh.o gen/uuidutil.o

libgen = gen/gh.o gen/uuidutil.o

libcore = core/chnl_sm.o core/msg_sm.o core/io_sm.o core/tiomap3430.o \

		core/tiomap3430_pwr.o core/tiomap_io.o \

		core/ue_deh.o core/wdt.o core/dsp-clock.o core/sync.o

* Eliminate general services and libraries - use or extend existing kernel

  libraries instead (e.g. gcf/lcm in nldr.c, global helpers in gen/)

* Eliminate direct manipulation of OMAP_SYSC_BASE

* Eliminate list.h : seem like a redundant wrapper to existing kernel lists

* Eliminate DSP_SUCCEEDED macros and their imposed redundant indentations

  (adopt the kernel way of checking for return values)

* Audit interfaces exposed to user space

/* DEH Manager: only one created per board: */

struct deh_mgr {

	struct bridge_dev_context *hbridge_context;	/* Bridge context. */

	struct bridge_dev_context *bridge_context;	/* Bridge context. */

	struct ntfy_object *ntfy_obj;	/* NTFY object */

	/* MMU Fault DPC */

#ifndef _MSG_SM_

#define _MSG_SM_

#include <dspbridge/list.h>

#include <linux/list.h>

#include <dspbridge/msgdefs.h>

/*

	/* Function interface to Bridge driver */

	struct bridge_drv_interface *intf_fxns;

	struct io_mgr *hio_mgr;	/* IO manager */

	struct lst_list *queue_list;	/* List of MSG_QUEUEs */

	struct io_mgr *iomgr;		/* IO manager */

	struct list_head queue_list;	/* List of MSG_QUEUEs */

	spinlock_t msg_mgr_lock;	/* For critical sections */

	/* Signalled when MsgFrame is available */

	struct sync_object *sync_event;

	struct lst_list *msg_free_list;	/* Free MsgFrames ready to be filled */

	struct lst_list *msg_used_list;	/* MsgFrames ready to go to DSP */

	struct list_head msg_free_list;	/* Free MsgFrames ready to be filled */

	struct list_head msg_used_list;	/* MsgFrames ready to go to DSP */

	u32 msgs_pending;	/* # of queued messages to go to DSP */

	u32 max_msgs;		/* Max # of msgs that fit in buffer */

	msg_onexit on_exit;	/* called when RMS_EXIT is received */

 */

struct msg_queue {

	struct list_head list_elem;

	struct msg_mgr *hmsg_mgr;

	struct msg_mgr *msg_mgr;

	u32 max_msgs;		/* Node message depth */

	u32 msgq_id;		/* Node environment pointer */

	struct lst_list *msg_free_list;	/* Free MsgFrames ready to be filled */

	struct list_head msg_free_list;	/* Free MsgFrames ready to be filled */

	/* Filled MsgFramess waiting to be read */

	struct lst_list *msg_used_list;

	struct list_head msg_used_list;

	void *arg;		/* Handle passed to mgr on_exit callback */

	struct sync_object *sync_event;	/* Signalled when message is ready */

	struct sync_object *sync_done;	/* For synchronizing cleanup */

/* This Bridge driver's device context: */

struct bridge_dev_context {

	struct dev_object *hdev_obj;	/* Handle to Bridge device object. */

	u32 dw_dsp_base_addr;	/* Arm's API to DSP virt base addr */

	struct dev_object *dev_obj;	/* Handle to Bridge device object. */

	u32 dsp_base_addr;	/* Arm's API to DSP virt base addr */

	/*

	 * DSP External memory prog address as seen virtually by the OS on

	 * the host side.

	 */

	u32 dw_dsp_ext_base_addr;	/* See the comment above */

	u32 dw_api_reg_base;	/* API mem map'd registers */

	void __iomem *dw_dsp_mmu_base;	/* DSP MMU Mapped registers */

	u32 dw_api_clk_base;	/* CLK Registers */

	u32 dw_dsp_clk_m2_base;	/* DSP Clock Module m2 */

	u32 dw_public_rhea;	/* Pub Rhea */

	u32 dw_int_addr;	/* MB INTR reg */

	u32 dw_tc_endianism;	/* TC Endianism register */

	u32 dw_test_base;	/* DSP MMU Mapped registers */

	u32 dw_self_loop;	/* Pointer to the selfloop */

	u32 dw_dsp_start_add;	/* API Boot vector */

	u32 dw_internal_size;	/* Internal memory size */

	u32 dsp_ext_base_addr;	/* See the comment above */

	u32 api_reg_base;	/* API mem map'd registers */

	void __iomem *dsp_mmu_base;	/* DSP MMU Mapped registers */

	u32 api_clk_base;	/* CLK Registers */

	u32 dsp_clk_m2_base;	/* DSP Clock Module m2 */

	u32 public_rhea;	/* Pub Rhea */

	u32 int_addr;		/* MB INTR reg */

	u32 tc_endianism;	/* TC Endianism register */

	u32 test_base;		/* DSP MMU Mapped registers */

	u32 self_loop;		/* Pointer to the selfloop */

	u32 dsp_start_add;	/* API Boot vector */

	u32 internal_size;	/* Internal memory size */

	struct omap_mbox *mbox;		/* Mail box handle */

	 */

	/* DMMU TLB entries */

	struct bridge_ioctl_extproc atlb_entry[BRDIOCTL_NUMOFMMUTLB];

	u32 dw_brd_state;       /* Last known board state. */

	u32 brd_state;       /* Last known board state. */

	/* TC Settings */

	bool tc_word_swap_on;	/* Traffic Controller Word Swap */