Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 59a69575 authored by Harshdeep Dhatt's avatar Harshdeep Dhatt Committed by Gerrit - the friendly Code Review server
Browse files

msm: kgsl: Use fence mechanism for A6XX preemption register writes 



This is an alternative method for successfully writing to preemption
registers if device is in IFPC. The A6XX preemption registers are
fenced. That means, when we write to these registers and if the device
is in IFPC, we can poll the fence status register to make sure the GPU
is up and write went through. The preemption registers are saved/restored
across IFPC. This ensures that if device goes to IFPC during one of
these register writes, the writes will not be lost.

Change-Id: Id09ec236b19da1491a588bfe063cfed220ffaf62
Signed-off-by: default avatarHarshdeep Dhatt <hdhatt@codeaurora.org>
parent 8f78d5fb

drivers/gpu/msm/adreno.h

+6 −0
Original line number Diff line number Diff line
@@ -612,6 +612,12 @@ enum adreno_regs { 
	ADRENO_REG_CP_PROTECT_REG_0,

	ADRENO_REG_CP_CONTEXT_SWITCH_SMMU_INFO_LO,

	ADRENO_REG_CP_CONTEXT_SWITCH_SMMU_INFO_HI,

	ADRENO_REG_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO,

	ADRENO_REG_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI,

	ADRENO_REG_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO,

	ADRENO_REG_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI,

	ADRENO_REG_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO,

	ADRENO_REG_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI,

	ADRENO_REG_RBBM_STATUS,

	ADRENO_REG_RBBM_STATUS3,

	ADRENO_REG_RBBM_PERFCTR_CTL,

drivers/gpu/msm/adreno_a6xx.c

+16 −0
Original line number Diff line number Diff line
@@ -3069,6 +3069,22 @@ static unsigned int a6xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
			A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_CONTEXT_SWITCH_SMMU_INFO_HI,

			A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI),

	ADRENO_REG_DEFINE(

		ADRENO_REG_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO,

			A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO),

	ADRENO_REG_DEFINE(

		ADRENO_REG_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI,

			A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI),

	ADRENO_REG_DEFINE(

		ADRENO_REG_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO,

			A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO),

	ADRENO_REG_DEFINE(

		ADRENO_REG_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI,

			A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO,

			A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI,

			A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_STATUS, A6XX_RBBM_STATUS),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_STATUS3, A6XX_RBBM_STATUS3),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_CTL, A6XX_RBBM_PERFCTR_CNTL),

drivers/gpu/msm/adreno_a6xx_preempt.c

+29 −15
Original line number Diff line number Diff line
@@ -275,20 +275,32 @@ void a6xx_preemption_trigger(struct adreno_device *adreno_dev) 
	kgsl_sharedmem_writel(device, &iommu->smmu_info,

		PREEMPT_SMMU_RECORD(context_idr), contextidr);



	kgsl_regwrite(device,

		A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO,

		lower_32_bits(next->preemption_desc.gpuaddr));

	kgsl_regwrite(device,

		A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI,

		upper_32_bits(next->preemption_desc.gpuaddr));



	kgsl_sharedmem_readq(&device->scratch, &gpuaddr,

		SCRATCH_PREEMPTION_CTXT_RESTORE_ADDR_OFFSET(next->id));



	kgsl_regwrite(device, A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO,

		lower_32_bits(gpuaddr));

	kgsl_regwrite(device, A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI,

		upper_32_bits(gpuaddr));

	/*

	 * Fenced writes on this path will make sure the GPU is woken up

	 * in case it was power collapsed by the GMU.

	 */

	adreno_gmu_fenced_write(adreno_dev,

		ADRENO_REG_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO,

		lower_32_bits(next->preemption_desc.gpuaddr),

		FENCE_STATUS_WRITEDROPPED1_MASK);



	adreno_gmu_fenced_write(adreno_dev,

		ADRENO_REG_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI,

		upper_32_bits(next->preemption_desc.gpuaddr),

		FENCE_STATUS_WRITEDROPPED1_MASK);



	adreno_gmu_fenced_write(adreno_dev,

		ADRENO_REG_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO,

		lower_32_bits(gpuaddr),

		FENCE_STATUS_WRITEDROPPED1_MASK);



	adreno_gmu_fenced_write(adreno_dev,

		ADRENO_REG_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI,

		upper_32_bits(gpuaddr),

		FENCE_STATUS_WRITEDROPPED1_MASK);



	adreno_dev->next_rb = next;
@@ -301,10 +313,12 @@ void a6xx_preemption_trigger(struct adreno_device *adreno_dev) 
	adreno_set_preempt_state(adreno_dev, ADRENO_PREEMPT_TRIGGERED);



	/* Trigger the preemption */

	adreno_writereg(adreno_dev, ADRENO_REG_CP_PREEMPT,

			((preempt_level << 6) & 0xC0) |

	adreno_gmu_fenced_write(adreno_dev,

		ADRENO_REG_CP_PREEMPT,

		(((preempt_level << 6) & 0xC0) |

		((skipsaverestore << 9) & 0x200) |

			((usesgmem << 8) & 0x100) | 0x1);

		((usesgmem << 8) & 0x100) | 0x1),

		FENCE_STATUS_WRITEDROPPED1_MASK);

}



void a6xx_preemption_callback(struct adreno_device *adreno_dev, int bit)