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Commit 597db6f3 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/dead-code' into next 

* pci/dead-code:
  PCI: Make local functions static
  PCI: Remove unused alloc_pci_dev()
  PCI: Remove unused pci_renumber_slot()
  PCI: Remove unused pcie_aspm_enabled()
  PCI: Remove unused pci_vpd_truncate()
  PCI: Remove unused ID-Based Ordering support
  PCI: Remove unused Optimized Buffer Flush/Fill support
  PCI: Remove unused Latency Tolerance Reporting support
  PCI: Removed unused parts of Page Request Interface support

Conflicts:
	drivers/pci/pci.c
	include/linux/pci.h
parents 6b9bd1e3 0b950f0f

drivers/pci/access.c

+0 −24
Original line number Diff line number Diff line
@@ -380,30 +380,6 @@ int pci_vpd_pci22_init(struct pci_dev *dev) 
	return 0;

}



/**

 * pci_vpd_truncate - Set available Vital Product Data size

 * @dev:	pci device struct

 * @size:	available memory in bytes

 *

 * Adjust size of available VPD area.

 */

int pci_vpd_truncate(struct pci_dev *dev, size_t size)

{

	if (!dev->vpd)

		return -EINVAL;



	/* limited by the access method */

	if (size > dev->vpd->len)

		return -EINVAL;



	dev->vpd->len = size;

	if (dev->vpd->attr)

		dev->vpd->attr->size = size;



	return 0;

}

EXPORT_SYMBOL(pci_vpd_truncate);



/**

 * pci_cfg_access_lock - Lock PCI config reads/writes

 * @dev:	pci device struct

drivers/pci/ats.c

+0 −82
Original line number Diff line number Diff line
@@ -234,27 +234,6 @@ void pci_disable_pri(struct pci_dev *pdev) 
}

EXPORT_SYMBOL_GPL(pci_disable_pri);



/**

 * pci_pri_enabled - Checks if PRI capability is enabled

 * @pdev: PCI device structure

 *

 * Returns true if PRI is enabled on the device, false otherwise

 */

bool pci_pri_enabled(struct pci_dev *pdev)

{

	u16 control;

	int pos;



	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);

	if (!pos)

		return false;



	pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);



	return (control & PCI_PRI_CTRL_ENABLE) ? true : false;

}

EXPORT_SYMBOL_GPL(pci_pri_enabled);



/**

 * pci_reset_pri - Resets device's PRI state

 * @pdev: PCI device structure
@@ -282,67 +261,6 @@ int pci_reset_pri(struct pci_dev *pdev) 
	return 0;

}

EXPORT_SYMBOL_GPL(pci_reset_pri);



/**

 * pci_pri_stopped - Checks whether the PRI capability is stopped

 * @pdev: PCI device structure

 *

 * Returns true if the PRI capability on the device is disabled and the

 * device has no outstanding PRI requests, false otherwise. The device

 * indicates this via the STOPPED bit in the status register of the

 * capability.

 * The device internal state can be cleared by resetting the PRI state

 * with pci_reset_pri(). This can force the capability into the STOPPED

 * state.

 */

bool pci_pri_stopped(struct pci_dev *pdev)

{

	u16 control, status;

	int pos;



	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);

	if (!pos)

		return true;



	pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);

	pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);



	if (control & PCI_PRI_CTRL_ENABLE)

		return false;



	return (status & PCI_PRI_STATUS_STOPPED) ? true : false;

}

EXPORT_SYMBOL_GPL(pci_pri_stopped);



/**

 * pci_pri_status - Request PRI status of a device

 * @pdev: PCI device structure

 *

 * Returns negative value on failure, status on success. The status can

 * be checked against status-bits. Supported bits are currently:

 * PCI_PRI_STATUS_RF:      Response failure

 * PCI_PRI_STATUS_UPRGI:   Unexpected Page Request Group Index

 * PCI_PRI_STATUS_STOPPED: PRI has stopped

 */

int pci_pri_status(struct pci_dev *pdev)

{

	u16 status, control;

	int pos;



	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);

	if (!pos)

		return -EINVAL;



	pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);

	pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);



	/* Stopped bit is undefined when enable == 1, so clear it */

	if (control & PCI_PRI_CTRL_ENABLE)

		status &= ~PCI_PRI_STATUS_STOPPED;



	return status;

}

EXPORT_SYMBOL_GPL(pci_pri_status);

#endif /* CONFIG_PCI_PRI */



#ifdef CONFIG_PCI_PASID

drivers/pci/hotplug/pciehp.h

+0 −1
Original line number Diff line number Diff line
@@ -43,7 +43,6 @@ 
extern bool pciehp_poll_mode;

extern int pciehp_poll_time;

extern bool pciehp_debug;

extern bool pciehp_force;



#define dbg(format, arg...)						\

do {									\

drivers/pci/hotplug/pciehp_core.c

+1 −1
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ 
bool pciehp_debug;

bool pciehp_poll_mode;

int pciehp_poll_time;

bool pciehp_force;

static bool pciehp_force;



#define DRIVER_VERSION	"0.4"

#define DRIVER_AUTHOR	"Dan Zink <dan.zink@compaq.com>, Greg Kroah-Hartman <greg@kroah.com>, Dely Sy <dely.l.sy@intel.com>"

drivers/pci/pci.c

+25 −261
Original line number Diff line number Diff line
@@ -682,6 +682,28 @@ static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) 
	return error;

}



/**

 * pci_wakeup - Wake up a PCI device

 * @pci_dev: Device to handle.

 * @ign: ignored parameter

 */

static int pci_wakeup(struct pci_dev *pci_dev, void *ign)

{

	pci_wakeup_event(pci_dev);

	pm_request_resume(&pci_dev->dev);

	return 0;

}



/**

 * pci_wakeup_bus - Walk given bus and wake up devices on it

 * @bus: Top bus of the subtree to walk.

 */

static void pci_wakeup_bus(struct pci_bus *bus)

{

	if (bus)

		pci_walk_bus(bus, pci_wakeup, NULL);

}



/**

 * __pci_start_power_transition - Start power transition of a PCI device

 * @dev: PCI device to handle.
@@ -1110,7 +1132,8 @@ EXPORT_SYMBOL_GPL(pci_store_saved_state); 
 * @dev: PCI device that we're dealing with

 * @state: Saved state returned from pci_store_saved_state()

 */

int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)

static int pci_load_saved_state(struct pci_dev *dev,

				struct pci_saved_state *state)

{

	struct pci_cap_saved_data *cap;
@@ -1138,7 +1161,6 @@ int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state) 
	dev->state_saved = true;

	return 0;

}

EXPORT_SYMBOL_GPL(pci_load_saved_state);



/**

 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
@@ -1570,27 +1592,6 @@ void pci_pme_wakeup_bus(struct pci_bus *bus) 
		pci_walk_bus(bus, pci_pme_wakeup, (void *)true);

}



/**

 * pci_wakeup - Wake up a PCI device

 * @pci_dev: Device to handle.

 * @ign: ignored parameter

 */

static int pci_wakeup(struct pci_dev *pci_dev, void *ign)

{

	pci_wakeup_event(pci_dev);

	pm_request_resume(&pci_dev->dev);

	return 0;

}



/**

 * pci_wakeup_bus - Walk given bus and wake up devices on it

 * @bus: Top bus of the subtree to walk.

 */

void pci_wakeup_bus(struct pci_bus *bus)

{

	if (bus)

		pci_walk_bus(bus, pci_wakeup, NULL);

}



/**

 * pci_pme_capable - check the capability of PCI device to generate PME#
@@ -1804,7 +1805,7 @@ int pci_wake_from_d3(struct pci_dev *dev, bool enable) 
 * If the platform can't manage @dev, return the deepest state from which it

 * can generate wake events, based on any available PME info.

 */

pci_power_t pci_target_state(struct pci_dev *dev)

static pci_power_t pci_target_state(struct pci_dev *dev)

{

	pci_power_t target_state = PCI_D3hot;
@@ -2168,242 +2169,6 @@ void pci_configure_ari(struct pci_dev *dev) 
	}

}



/**

 * pci_enable_ido - enable ID-based Ordering on a device

 * @dev: the PCI device

 * @type: which types of IDO to enable

 *

 * Enable ID-based ordering on @dev.  @type can contain the bits

 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate

 * which types of transactions are allowed to be re-ordered.

 */

void pci_enable_ido(struct pci_dev *dev, unsigned long type)

{

	u16 ctrl = 0;



	if (type & PCI_EXP_IDO_REQUEST)

		ctrl |= PCI_EXP_DEVCTL2_IDO_REQ_EN;

	if (type & PCI_EXP_IDO_COMPLETION)

		ctrl |= PCI_EXP_DEVCTL2_IDO_CMP_EN;

	if (ctrl)

		pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, ctrl);

}

EXPORT_SYMBOL(pci_enable_ido);



/**

 * pci_disable_ido - disable ID-based ordering on a device

 * @dev: the PCI device

 * @type: which types of IDO to disable

 */

void pci_disable_ido(struct pci_dev *dev, unsigned long type)

{

	u16 ctrl = 0;



	if (type & PCI_EXP_IDO_REQUEST)

		ctrl |= PCI_EXP_DEVCTL2_IDO_REQ_EN;

	if (type & PCI_EXP_IDO_COMPLETION)

		ctrl |= PCI_EXP_DEVCTL2_IDO_CMP_EN;

	if (ctrl)

		pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, ctrl);

}

EXPORT_SYMBOL(pci_disable_ido);



/**

 * pci_enable_obff - enable optimized buffer flush/fill

 * @dev: PCI device

 * @type: type of signaling to use

 *

 * Try to enable @type OBFF signaling on @dev.  It will try using WAKE#

 * signaling if possible, falling back to message signaling only if

 * WAKE# isn't supported.  @type should indicate whether the PCIe link

 * be brought out of L0s or L1 to send the message.  It should be either

 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.

 *

 * If your device can benefit from receiving all messages, even at the

 * power cost of bringing the link back up from a low power state, use

 * %PCI_EXP_OBFF_SIGNAL_ALWAYS.  Otherwise, use %PCI_OBFF_SIGNAL_L0 (the

 * preferred type).

 *

 * RETURNS:

 * Zero on success, appropriate error number on failure.

 */

int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)

{

	u32 cap;

	u16 ctrl;

	int ret;



	pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);

	if (!(cap & PCI_EXP_DEVCAP2_OBFF_MASK))

		return -ENOTSUPP; /* no OBFF support at all */



	/* Make sure the topology supports OBFF as well */

	if (dev->bus->self) {

		ret = pci_enable_obff(dev->bus->self, type);

		if (ret)

			return ret;

	}



	pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctrl);

	if (cap & PCI_EXP_DEVCAP2_OBFF_WAKE)

		ctrl |= PCI_EXP_DEVCTL2_OBFF_WAKE_EN;

	else {

		switch (type) {

		case PCI_EXP_OBFF_SIGNAL_L0:

			if (!(ctrl & PCI_EXP_DEVCTL2_OBFF_WAKE_EN))

				ctrl |= PCI_EXP_DEVCTL2_OBFF_MSGA_EN;

			break;

		case PCI_EXP_OBFF_SIGNAL_ALWAYS:

			ctrl &= ~PCI_EXP_DEVCTL2_OBFF_WAKE_EN;

			ctrl |= PCI_EXP_DEVCTL2_OBFF_MSGB_EN;

			break;

		default:

			WARN(1, "bad OBFF signal type\n");

			return -ENOTSUPP;

		}

	}

	pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, ctrl);



	return 0;

}

EXPORT_SYMBOL(pci_enable_obff);



/**

 * pci_disable_obff - disable optimized buffer flush/fill

 * @dev: PCI device

 *

 * Disable OBFF on @dev.

 */

void pci_disable_obff(struct pci_dev *dev)

{

	pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2,

				   PCI_EXP_DEVCTL2_OBFF_WAKE_EN);

}

EXPORT_SYMBOL(pci_disable_obff);



/**

 * pci_ltr_supported - check whether a device supports LTR

 * @dev: PCI device

 *

 * RETURNS:

 * True if @dev supports latency tolerance reporting, false otherwise.

 */

static bool pci_ltr_supported(struct pci_dev *dev)

{

	u32 cap;



	pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);



	return cap & PCI_EXP_DEVCAP2_LTR;

}



/**

 * pci_enable_ltr - enable latency tolerance reporting

 * @dev: PCI device

 *

 * Enable LTR on @dev if possible, which means enabling it first on

 * upstream ports.

 *

 * RETURNS:

 * Zero on success, errno on failure.

 */

int pci_enable_ltr(struct pci_dev *dev)

{

	int ret;



	/* Only primary function can enable/disable LTR */

	if (PCI_FUNC(dev->devfn) != 0)

		return -EINVAL;



	if (!pci_ltr_supported(dev))

		return -ENOTSUPP;



	/* Enable upstream ports first */

	if (dev->bus->self) {

		ret = pci_enable_ltr(dev->bus->self);

		if (ret)

			return ret;

	}



	return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,

					PCI_EXP_DEVCTL2_LTR_EN);

}

EXPORT_SYMBOL(pci_enable_ltr);



/**

 * pci_disable_ltr - disable latency tolerance reporting

 * @dev: PCI device

 */

void pci_disable_ltr(struct pci_dev *dev)

{

	/* Only primary function can enable/disable LTR */

	if (PCI_FUNC(dev->devfn) != 0)

		return;



	if (!pci_ltr_supported(dev))

		return;



	pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2,

				   PCI_EXP_DEVCTL2_LTR_EN);

}

EXPORT_SYMBOL(pci_disable_ltr);



static int __pci_ltr_scale(int *val)

{

	int scale = 0;



	while (*val > 1023) {

		*val = (*val + 31) / 32;

		scale++;

	}

	return scale;

}



/**

 * pci_set_ltr - set LTR latency values

 * @dev: PCI device

 * @snoop_lat_ns: snoop latency in nanoseconds

 * @nosnoop_lat_ns: nosnoop latency in nanoseconds

 *

 * Figure out the scale and set the LTR values accordingly.

 */

int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)

{

	int pos, ret, snoop_scale, nosnoop_scale;

	u16 val;



	if (!pci_ltr_supported(dev))

		return -ENOTSUPP;



	snoop_scale = __pci_ltr_scale(&snoop_lat_ns);

	nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);



	if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||

	    nosnoop_lat_ns > PCI_LTR_VALUE_MASK)

		return -EINVAL;



	if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||

	    (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))

		return -EINVAL;



	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);

	if (!pos)

		return -ENOTSUPP;



	val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;

	ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);

	if (ret != 4)

		return -EIO;



	val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;

	ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);

	if (ret != 4)

		return -EIO;



	return 0;

}

EXPORT_SYMBOL(pci_set_ltr);



static int pci_acs_enable;



/**
@@ -4482,7 +4247,6 @@ EXPORT_SYMBOL(pci_restore_state); 
EXPORT_SYMBOL(pci_pme_capable);

EXPORT_SYMBOL(pci_pme_active);

EXPORT_SYMBOL(pci_wake_from_d3);

EXPORT_SYMBOL(pci_target_state);

EXPORT_SYMBOL(pci_prepare_to_sleep);

EXPORT_SYMBOL(pci_back_from_sleep);

EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);