Loading drivers/gpu/drm/msm/sde/sde_crtc.c +9 −4 Original line number Diff line number Diff line Loading @@ -2527,13 +2527,16 @@ static int sde_crtc_atomic_check(struct drm_crtc *crtc, } for (i = 1; i < SSPP_MAX; i++) { if (pipe_staged[i] && is_sde_plane_virtual(pipe_staged[i]->plane)) { if (pipe_staged[i]) { sde_plane_clear_multirect(pipe_staged[i]); if (is_sde_plane_virtual(pipe_staged[i]->plane)) { SDE_ERROR("invalid use of virtual plane: %d\n", pipe_staged[i]->plane->base.id); goto end; } } } /* assign mixer stages based on sorted zpos property */ sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL); Loading Loading @@ -3045,6 +3048,8 @@ static int _sde_debugfs_status_show(struct seq_file *s, void *data) seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n", state->crtc_x, state->crtc_y, state->crtc_w, state->crtc_h); seq_printf(s, "\tmultirect: mode: %d index: %d\n", pstate->multirect_mode, pstate->multirect_index); seq_puts(s, "\n"); } Loading drivers/gpu/drm/msm/sde/sde_hw_sspp.c +19 −16 Original line number Diff line number Diff line Loading @@ -299,7 +299,7 @@ static void sde_hw_sspp_setup_format(struct sde_hw_pipe *ctx, { struct sde_hw_blk_reg_map *c; u32 chroma_samp, unpack, src_format; u32 secure = 0; u32 secure = 0, secure_bit_mask; u32 opmode = 0; u32 op_mode_off, unpack_pat_off, format_off; u32 idx; Loading @@ -311,10 +311,12 @@ static void sde_hw_sspp_setup_format(struct sde_hw_pipe *ctx, op_mode_off = SSPP_SRC_OP_MODE; unpack_pat_off = SSPP_SRC_UNPACK_PATTERN; format_off = SSPP_SRC_FORMAT; secure_bit_mask = (rect_mode == SDE_SSPP_RECT_SOLO) ? 0xF : 0x5; } else { op_mode_off = SSPP_SRC_OP_MODE_REC1; unpack_pat_off = SSPP_SRC_UNPACK_PATTERN_REC1; format_off = SSPP_SRC_FORMAT_REC1; secure_bit_mask = 0xA; } c = &ctx->hw; Loading @@ -322,16 +324,11 @@ static void sde_hw_sspp_setup_format(struct sde_hw_pipe *ctx, opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD | MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE); if (flags & SDE_SSPP_SECURE_OVERLAY_SESSION) { secure = SDE_REG_READ(c, SSPP_SRC_ADDR_SW_STATUS + idx); if (rect_mode == SDE_SSPP_RECT_SOLO) secure |= 0xF; else if (rect_mode == SDE_SSPP_RECT_0) secure |= 0x5; else if (rect_mode == SDE_SSPP_RECT_1) secure |= 0xA; } if (flags & SDE_SSPP_SECURE_OVERLAY_SESSION) secure |= secure_bit_mask; else secure &= ~secure_bit_mask; if (flags & SDE_SSPP_FLIP_LR) opmode |= MDSS_MDP_OP_FLIP_LR; Loading Loading @@ -803,11 +800,17 @@ static void sde_hw_sspp_setup_rects(struct sde_hw_pipe *ctx, ystride1 = SDE_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx); if (rect_index == SDE_SSPP_RECT_0) { ystride0 |= cfg->layout.plane_pitch[0]; ystride1 |= cfg->layout.plane_pitch[2]; ystride0 = (ystride0 & 0xFFFF0000) | (cfg->layout.plane_pitch[0] & 0x0000FFFF); ystride1 = (ystride1 & 0xFFFF0000)| (cfg->layout.plane_pitch[2] & 0x0000FFFF); } else { ystride0 |= cfg->layout.plane_pitch[0] << 16; ystride1 |= cfg->layout.plane_pitch[2] << 16; ystride0 = (ystride0 & 0x0000FFFF) | ((cfg->layout.plane_pitch[0] << 16) & 0xFFFF0000); ystride1 = (ystride1 & 0x0000FFFF) | ((cfg->layout.plane_pitch[2] << 16) & 0xFFFF0000); } } Loading drivers/gpu/drm/msm/sde/sde_plane.c +535 −482 File changed.Preview size limit exceeded, changes collapsed. Show changes drivers/gpu/drm/msm/sde/sde_plane.h +6 −1 Original line number Diff line number Diff line Loading @@ -207,9 +207,14 @@ struct drm_plane *sde_plane_init(struct drm_device *dev, * against hw limitations * @plane: drm plate states of the multirect pair */ int sde_plane_validate_multirect_v2(struct sde_multirect_plane_states *plane); /** * sde_plane_clear_multirect - clear multirect bits for the given pipe * @drm_state: Pointer to DRM plane state */ void sde_plane_clear_multirect(const struct drm_plane_state *drm_state); /** * sde_plane_wait_input_fence - wait for input fence object * @plane: Pointer to DRM plane object Loading Loading
drivers/gpu/drm/msm/sde/sde_crtc.c +9 −4 Original line number Diff line number Diff line Loading @@ -2527,13 +2527,16 @@ static int sde_crtc_atomic_check(struct drm_crtc *crtc, } for (i = 1; i < SSPP_MAX; i++) { if (pipe_staged[i] && is_sde_plane_virtual(pipe_staged[i]->plane)) { if (pipe_staged[i]) { sde_plane_clear_multirect(pipe_staged[i]); if (is_sde_plane_virtual(pipe_staged[i]->plane)) { SDE_ERROR("invalid use of virtual plane: %d\n", pipe_staged[i]->plane->base.id); goto end; } } } /* assign mixer stages based on sorted zpos property */ sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL); Loading Loading @@ -3045,6 +3048,8 @@ static int _sde_debugfs_status_show(struct seq_file *s, void *data) seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n", state->crtc_x, state->crtc_y, state->crtc_w, state->crtc_h); seq_printf(s, "\tmultirect: mode: %d index: %d\n", pstate->multirect_mode, pstate->multirect_index); seq_puts(s, "\n"); } Loading
drivers/gpu/drm/msm/sde/sde_hw_sspp.c +19 −16 Original line number Diff line number Diff line Loading @@ -299,7 +299,7 @@ static void sde_hw_sspp_setup_format(struct sde_hw_pipe *ctx, { struct sde_hw_blk_reg_map *c; u32 chroma_samp, unpack, src_format; u32 secure = 0; u32 secure = 0, secure_bit_mask; u32 opmode = 0; u32 op_mode_off, unpack_pat_off, format_off; u32 idx; Loading @@ -311,10 +311,12 @@ static void sde_hw_sspp_setup_format(struct sde_hw_pipe *ctx, op_mode_off = SSPP_SRC_OP_MODE; unpack_pat_off = SSPP_SRC_UNPACK_PATTERN; format_off = SSPP_SRC_FORMAT; secure_bit_mask = (rect_mode == SDE_SSPP_RECT_SOLO) ? 0xF : 0x5; } else { op_mode_off = SSPP_SRC_OP_MODE_REC1; unpack_pat_off = SSPP_SRC_UNPACK_PATTERN_REC1; format_off = SSPP_SRC_FORMAT_REC1; secure_bit_mask = 0xA; } c = &ctx->hw; Loading @@ -322,16 +324,11 @@ static void sde_hw_sspp_setup_format(struct sde_hw_pipe *ctx, opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD | MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE); if (flags & SDE_SSPP_SECURE_OVERLAY_SESSION) { secure = SDE_REG_READ(c, SSPP_SRC_ADDR_SW_STATUS + idx); if (rect_mode == SDE_SSPP_RECT_SOLO) secure |= 0xF; else if (rect_mode == SDE_SSPP_RECT_0) secure |= 0x5; else if (rect_mode == SDE_SSPP_RECT_1) secure |= 0xA; } if (flags & SDE_SSPP_SECURE_OVERLAY_SESSION) secure |= secure_bit_mask; else secure &= ~secure_bit_mask; if (flags & SDE_SSPP_FLIP_LR) opmode |= MDSS_MDP_OP_FLIP_LR; Loading Loading @@ -803,11 +800,17 @@ static void sde_hw_sspp_setup_rects(struct sde_hw_pipe *ctx, ystride1 = SDE_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx); if (rect_index == SDE_SSPP_RECT_0) { ystride0 |= cfg->layout.plane_pitch[0]; ystride1 |= cfg->layout.plane_pitch[2]; ystride0 = (ystride0 & 0xFFFF0000) | (cfg->layout.plane_pitch[0] & 0x0000FFFF); ystride1 = (ystride1 & 0xFFFF0000)| (cfg->layout.plane_pitch[2] & 0x0000FFFF); } else { ystride0 |= cfg->layout.plane_pitch[0] << 16; ystride1 |= cfg->layout.plane_pitch[2] << 16; ystride0 = (ystride0 & 0x0000FFFF) | ((cfg->layout.plane_pitch[0] << 16) & 0xFFFF0000); ystride1 = (ystride1 & 0x0000FFFF) | ((cfg->layout.plane_pitch[2] << 16) & 0xFFFF0000); } } Loading
drivers/gpu/drm/msm/sde/sde_plane.c +535 −482 File changed.Preview size limit exceeded, changes collapsed. Show changes
drivers/gpu/drm/msm/sde/sde_plane.h +6 −1 Original line number Diff line number Diff line Loading @@ -207,9 +207,14 @@ struct drm_plane *sde_plane_init(struct drm_device *dev, * against hw limitations * @plane: drm plate states of the multirect pair */ int sde_plane_validate_multirect_v2(struct sde_multirect_plane_states *plane); /** * sde_plane_clear_multirect - clear multirect bits for the given pipe * @drm_state: Pointer to DRM plane state */ void sde_plane_clear_multirect(const struct drm_plane_state *drm_state); /** * sde_plane_wait_input_fence - wait for input fence object * @plane: Pointer to DRM plane object Loading