Merge branches 'pci/host-armada', 'pci/host-designware', 'pci/host-hv',...

and thus inherits all the common properties defined in designware-pcie.txt.

Required properties:

- compatible: "fsl,imx6q-pcie"

- reg: base addresse and length of the pcie controller

- compatible: "fsl,imx6q-pcie", "fsl,imx6sx-pcie", "fsl,imx6qp-pcie"

- reg: base address and length of the PCIe controller

- interrupts: A list of interrupt outputs of the controller. Must contain an

  entry for each entry in the interrupt-names property.

- interrupt-names: Must include the following entries:

- fsl,tx-deemph-gen2-6db: Gen2 (6db) De-emphasis value. Default: 20

- fsl,tx-swing-full: Gen2 TX SWING FULL value. Default: 127

- fsl,tx-swing-low: TX launch amplitude swing_low value. Default: 127

- fsl,max-link-speed: Specify PCI gen for link capability. Must be '2' for

  gen2, otherwise will default to gen1. Note that the IMX6 LVDS clock outputs

  do not meet gen2 jitter requirements and thus for gen2 capability a gen2

  compliant clock generator should be used and configured.

- reset-gpio: Should specify the GPIO for controlling the PCI bus device reset

  signal. It's not polarity aware and defaults to active-low reset sequence

  (L=reset state, H=operation state).

- reset-gpio-active-high: If present then the reset sequence using the GPIO

  specified in the "reset-gpio" property is reversed (H=reset state,

  L=operation state).

Additional required properties for imx6sx-pcie:

- clock names: Must include the following additional entries:

	- "pcie_inbound_axi"

Example:

* Marvell Armada 7K/8K PCIe interface

This PCIe host controller is based on the Synopsis Designware PCIe IP

and thus inherits all the common properties defined in designware-pcie.txt.

Required properties:

- compatible: "marvell,armada8k-pcie"

- reg: must contain two register regions

   - the control register region

   - the config space region

- reg-names:

   - "ctrl" for the control register region

   - "config" for the config space region

- interrupts: Interrupt specifier for the PCIe controler

- clocks: reference to the PCIe controller clock

Example:

	pcie@f2600000 {

		compatible = "marvell,armada8k-pcie", "snps,dw-pcie";

		reg = <0 0xf2600000 0 0x10000>, <0 0xf6f00000 0 0x80000>;

		reg-names = "ctrl", "config";

		#address-cells = <3>;

		#size-cells = <2>;

		#interrupt-cells = <1>;

		device_type = "pci";

		dma-coherent;

		bus-range = <0 0xff>;

		ranges = <0x81000000 0 0xf9000000 0  0xf9000000 0 0x10000	/* downstream I/O */

			  0x82000000 0 0xf6000000 0  0xf6000000 0 0xf00000>;	/* non-prefetchable memory */

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

		num-lanes = <1>;

		clocks = <&cpm_syscon0 1 13>;

		status = "disabled";

	};

	phy-names: name of the Generic Keystine SerDes phy for PCI

	  - If boot loader already does PCI link establishment, then phys and

	    phy-names shouldn't be present.

	interrupts: platform interrupt for error interrupts.

Designware DT Properties not applicable for Keystone PCI

};

&pcie {

	/* active-low meaning opposite of regular PERST# active-low polarity */

	reset-gpio = <&gpio1 28 GPIO_ACTIVE_LOW>;

	/* active-high meaning opposite of regular PERST# active-low polarity */

	reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;

	reset-gpio-active-high;

	status = "okay";

};

				      "ldb_di0", "ldb_di1", "prg";

		};

		pcie: pcie@0x01000000 {

			compatible = "fsl,imx6qp-pcie", "snps,dw-pcie";

		};

	};

};