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Commit 58e6e781 authored by Jean Delvare's avatar Jean Delvare Committed by Mark M. Hoffman
Browse files

hwmon: (w83627ehf) Be more careful when changing VID input level 



The VID input level change has been reported to cause trouble. Be more
careful in this respect:
* Only change the level on the W83627EHF/EHG. The W83627DHG is more
  complex in this respect.
* Don't change the level if the VID pins are in output mode.
* Only set the level to TTL if VRM 9.x is used.

Signed-off-by: default avatarJean Delvare <khali@linux-fr.org>
Signed-off-by: default avatarMark M. Hoffman <mhoffman@lightlink.com>
parent ea67db4c

drivers/hwmon/w83627ehf.c

+22 −14
Original line number Diff line number Diff line
@@ -1276,23 +1276,31 @@ static int __devinit w83627ehf_probe(struct platform_device *pdev) 


	data->vrm = vid_which_vrm();

	superio_enter(sio_data->sioreg);

	/* Set VID input sensibility if needed. In theory the BIOS should

	   have set it, but in practice it's not always the case. */

	en_vrm10 = superio_inb(sio_data->sioreg, SIO_REG_EN_VRM10);

	if ((en_vrm10 & 0x08) && data->vrm != 100) {

		dev_warn(dev, "Setting VID input voltage to TTL\n");

	/* Read VID value */

	superio_select(sio_data->sioreg, W83627EHF_LD_HWM);

	if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80) {

		/* Set VID input sensibility if needed. In theory the BIOS

		   should have set it, but in practice it's not always the

		   case. We only do it for the W83627EHF/EHG because the

		   W83627DHG is more complex in this respect. */

		if (sio_data->kind == w83627ehf) {

			en_vrm10 = superio_inb(sio_data->sioreg,

					       SIO_REG_EN_VRM10);

			if ((en_vrm10 & 0x08) && data->vrm == 90) {

				dev_warn(dev, "Setting VID input voltage to "

					 "TTL\n");

				superio_outb(sio_data->sioreg, SIO_REG_EN_VRM10,

					     en_vrm10 & ~0x08);

			} else if (!(en_vrm10 & 0x08) && data->vrm == 100) {

		dev_warn(dev, "Setting VID input voltage to VRM10\n");

				dev_warn(dev, "Setting VID input voltage to "

					 "VRM10\n");

				superio_outb(sio_data->sioreg, SIO_REG_EN_VRM10,

					     en_vrm10 | 0x08);

			}

	/* Read VID value */

	superio_select(sio_data->sioreg, W83627EHF_LD_HWM);

	if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80)

		}



		data->vid = superio_inb(sio_data->sioreg, SIO_REG_VID_DATA) & 0x3f;

	else {

	} else {

		dev_info(dev, "VID pins in output mode, CPU VID not "

			 "available\n");

		data->vid = 0x3f;