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Commit 58add9fc authored by Steve Glendinning's avatar Steve Glendinning Committed by David S. Miller
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smsc911x: enforce read-after-write timing restriction on eeprom access 



The LAN911x datasheet specifies a minimum delay of 45ns between a write
of E2P_DATA and any read.  This patch adds a single dummy read of
BYTE_TEST to enforce this timing constraint.

Signed-off-by: default avatarSteve Glendinning <steve.glendinning@smsc.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 54dc79fe

drivers/net/smsc911x.c

+5 −0
Original line number Original line Diff line number Diff line
@@ -1680,6 +1680,7 @@ static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata, 
					  u8 address, u8 data)

					  u8 address, u8 data)

{

{

	u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;

	u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;

	u32 temp;

	int ret;

	int ret;





	SMSC_TRACE(DRV, "address 0x%x, data 0x%x", address, data);

	SMSC_TRACE(DRV, "address 0x%x, data 0x%x", address, data);
@@ -1688,6 +1689,10 @@ static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata, 
	if (!ret) {

	if (!ret) {

		op = E2P_CMD_EPC_CMD_WRITE_ | address;

		op = E2P_CMD_EPC_CMD_WRITE_ | address;

		smsc911x_reg_write(pdata, E2P_DATA, (u32)data);

		smsc911x_reg_write(pdata, E2P_DATA, (u32)data);



		/* Workaround for hardware read-after-write restriction */

		temp = smsc911x_reg_read(pdata, BYTE_TEST);



		ret = smsc911x_eeprom_send_cmd(pdata, op);

		ret = smsc911x_eeprom_send_cmd(pdata, op);

	}

	}