Merge "ARM: dts: msm: Aligning DT files based on 4.9 kernel for msm8909w"

* CoreSight Components:

CoreSight components are compliant with the ARM CoreSight architecture

specification and can be connected in various topologies to suite a particular

SoCs tracing needs. These trace components can generally be classified as sinks,

links and sources. Trace data produced by one or more sources flows through the

intermediate links connecting the source to the currently selected sink. Each

CoreSight component device should use these properties to describe its hardware

characteristcs.

Required properties:

- compatible : name of the component used for driver matching, should be one of

	the following:

	"arm,coresight-tmc" for coresight tmc-etr or tmc-etf device,

	"arm,coresight-tpiu" for coresight tpiu device,

	"qcom,coresight-replicator" for coresight replicator device,

	"arm,coresight-funnel" for coresight funnel devices,

	"qcom,coresight-tpda" for coresight tpda device,

	"qcom,coresight-tpdm" for coresight tpdm device,

	"qcom,coresight-dbgui" for coresight dbgui device

	"arm,coresight-stm" for coresight stm trace device,

	"arm,coresight-etm" for coresight etm trace devices,

	"arm,coresight-etmv4" for coresight etmv4 trace devices,

	"qcom,coresight-csr" for coresight csr device,

	"arm,coresight-cti" for coresight cti devices,

	"qcom,coresight-hwevent" for coresight hardware event devices

	"arm,coresight-fuse" for coresight fuse v1 device,

	"arm,coresight-fuse-v2" for coresight fuse v2 device,

	"arm,coresight-fuse-v3" for coresight fuse v3 device,

	"qcom,coresight-remote-etm" for coresight remote processor etm trace device,

	"qcom,coresight-qpdi" for coresight qpdi device

- reg : physical base address and length of the register set(s) of the component.

	Not required for the following compatible string:

	- "qcom,coresight-remote-etm"

- reg-names : names corresponding to each reg property value.

	Not required for the following compatible string:

	- "qcom,coresight-remote-etm"

	The reg-names that need to be used with corresponding compatible string

	for a coresight device are:

	- for coresight tmc-etr or tmc-etf device:

		compatible : should be "arm,coresight-tmc"

		reg-names  : should be:

			"tmc-base" - physical base address of tmc configuration

				registers

			"bam-base" - physical base address of tmc-etr bam registers

	- for coresight tpiu device:

		compatible : should be "arm,coresight-tpiu"

		reg-names  : should be:

			"tpiu-base" - physical base address of tpiu registers

	- for coresight replicator device

		compatible : should be "qcom,coresight-replicator"

		reg-names  : should be:

			"replicator-base" - physical base address of replicator

				registers

	- for coresight funnel devices

		compatible : should be "arm,coresight-funnel"

		reg-names  : should be:

			"funnel-base" - physical base address of funnel registers

	- for coresight tpda trace device

		compatible : should be "qcom,coresight-tpda"

		reg-names  : should be:

			"tpda-base" - physical base address of tpda registers

	- for coresight tpdm trace device

		compatible : should be "qcom,coresight-tpdm"

		reg-names  : should be:

			"tpdm-base" - physical base address of tpdm registers

	- for coresight dbgui device:

		compatible : should be "qcom,coresight-dbgui"

		reg-names  : should be:

			"dbgui-base" - physical base address of dbgui registers

	- for coresight stm trace device

		compatible : should be "arm,coresight-stm"

		reg-names  : should be:

			"stm-base" - physical base address of stm configuration

				registers

			"stm-data-base" - physical base address of stm data registers

	- for coresight etm trace devices

		compatible : should be "arm,coresight-etm"

		reg-names  : should be:

			"etm-base" - physical base address of etm registers

	- for coresight etmv4 trace devices

		compatible : should be "arm,coresight-etmv4"

		reg-names  : should be:

			"etm-base" - physical base address of etmv4 registers

	- for coresight csr device:

		compatible : should be "qcom,coresight-csr"

		reg-names  : should be:

			"csr-base" - physical base address of csr registers

	- for coresight cti devices:

		compatible : should be "arm,coresight-cti"

		reg-names  : should be:

			"cti<num>-base" - physical base address of cti registers

	- for coresight hardware event devices:

		compatible : should be "qcom,coresight-hwevent"

		reg-names  : should be:

			"<ss-mux>" - physical base address of hardware event mux

				control registers where <ss-mux> is subsystem mux it

				represents

	- for coresight fuse device:

		compatible : should be "arm,coresight-fuse"

		reg-names  : should be:

			"fuse-base" - physical base address of fuse registers

			"nidnt-fuse-base" - physical base address of nidnt fuse registers

			"qpdi-fuse-base" - physical base address of qpdi fuse registers

	- for coresight qpdi device:

		compatible : should be "qcom,coresight-qpdi"

		reg-names  : should be:

			"qpdi-base" - physical base address of qpdi registers

- coresight-id : unique integer identifier for the component

- coresight-name : unique descriptive name of the component

- coresight-nr-inports : number of input ports on the component

Optional properties:

- coresight-outports : list of output port numbers of this component

- coresight-child-list : list of phandles pointing to the children of this

			 component

- coresight-child-ports : list of input port numbers of the children

- coresight-default-sink : represents the default compile time CoreSight sink

- coresight-ctis : list of ctis that this component interacts with

- qcom,cti-save : boolean, indicating cti context needs to be saved and restored

- qcom,cti-hwclk : boolean, indicating support of hardware clock to access cti

		   registers to be saved and restored

- qcom,cti-gpio-trigin : cti trigger input driven by gpio

- qcom,cti-gpio-trigout : cti trigger output sent to gpio

- qcom,pc-save : program counter save implemented

- qcom,blk-size : block size for tmc-etr to usb transfers

- qcom,memory-size : size of coherent memory to be allocated for tmc-etr buffer

- qcom,round-robin : indicates if per core etms are allowed round-robin access

		     by the funnel

- qcom,write-64bit : only 64bit data writes supported by stm

- qcom,data-barrier : barrier required for every stm data write to channel space

- <supply-name>-supply: phandle to the regulator device tree node. The required

			<supply-name> is "vdd" for SD card and "vdd-io" for SD

			I/O supply. Used for tpiu component

- qcom,<supply>-voltage-level : specifies voltage level for vdd supply. Should

				be specified in pairs (min, max) with units

				being uV. Here <supply> can be "vdd" for SD card

				vdd supply or "vdd-io" for SD I/O vdd supply.

- qcom,<supply>-current-level : specifies current load levels for vdd supply.

				Should be specified in pairs (lpm, hpm) with

				units being uA. Here <supply> can be "vdd" for

				SD card vdd supply or "vdd-io" for SD I/O vdd

				supply.

- qcom,hwevent-clks : list of clocks required by hardware event driver

- qcom,hwevent-regs : list of regulators required by hardware event driver

- qcom,byte-cntr-absent : specifies if the byte counter feature is absent on

			  the device. Only relevant in case of tmc-etr device.

- interrupts : <a b c> where a is 0 or 1 depending on if the interrupt is

		spi/ppi, b is the interrupt number and c is the mask,

- interrupt-names : a list of strings that map in order to the list of

		    interrupts specified in the 'interrupts' property.

- qcom,sg-enable : indicates whether scatter gather feature is supported for TMC

		   ETR configuration.

- qcom,force-reg-dump : boolean, indicate whether TMC register need to be dumped.

			Used for TMC component

- qcom,nidntsw : boolean, indicating NIDnT software debug or trace support

		 present. Used for tpiu component

- qcom,nidnthw : boolean, indicating NIDnT hardware sensing support present.

		 Used for tpiu component

  qcom,nidntsw and qcom,nidnthw are mutually exclusive properties, either of

  these may specified for tpiu component

- qcom,nidnt-swduart : boolean, indicating NIDnT swd uart support present. Used

		       for tpiu component

- qcom,nidnt-swdtrc : boolean, indicating NIDnT swd trace support present. Used

		      for tpiu component

- qcom,nidnt-jtag : boolean, indicating NIDnT jtag debug support present. Used

		    for tpiu component

- qcom,nidnt-spmi : boolean, indicating NIDnT spmi debug support present. Used

		    for tpiu component

- nidnt-gpio : specifies gpio for NIDnT hardware detection

- nidnt-gpio-polarity : specifies gpio polarity for NIDnT hardware detection

- pinctrl-names : names corresponding to the numbered pinctrl. The allowed

		  names are subset of the following: cti-trigin-pctrl,

		  cti-trigout-pctrl. Used for cti component

- pinctrl-<n>: list of pinctrl phandles for the different pinctrl states. Refer

	       to "Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt".

- qcom,funnel-save-restore : boolean, indicating funnel port needs to be disabled

			     for the ETM whose CPU is being powered down. The port

			     state is restored when CPU is powered up. Used for

			     funnel component.

- qcom,tmc-flush-powerdown : boolean, indicating trace data needs to be flushed before

			     powering down CPU. Used for TMC component.

- qcom,bc-elem-size : specifies the BC element size supported by each monitor

		      connected to the aggregator on each port. Should be specified

		      in pairs (port, bc element size).

- qcom,tc-elem-size : specifies the TC element size supported by each monitor

		      connected to the aggregator on each port. Should be specified

		      in pairs (port, tc element size).

- qcom,dsb-elem-size : specifies the DSB element size supported by each monitor

		       connected to the aggregator on each port. Should be specified

		       in pairs (port, dsb element size).

- qcom,cmb-elem-size : specifies the CMB element size supported by each monitor

		       connected to the aggregator on each port. Should be specified

		       in pairs (port, cmb element size).

- qcom,clk-enable: specifies whether additional clock bit needs to be set for

		   M4M TPDM.

- qcom,tpda-atid : specifies the ATID for TPDA.

- qcom,inst-id : QMI instance id for remote ETMs.

- qcom,noovrflw-enable : boolean, indicating whether no overflow bit needs to be

			 set in ETM stall control register.

- coresight-cti-cpu : cpu phandle for cpu cti, required when qcom,cti-save is true

- coresight-etm-cpu : specifies phandle for the cpu associated with the ETM device

- qcom,dbgui-addr-offset : indicates the offset of dbgui address registers

- qcom,dbgui-data-offset : indicates the offset of dbgui data registers

- qcom,dbgui-size : indicates the size of dbgui address and data registers

- qcom,pmic-carddetect-gpio : indicates the hotplug capabilities of the qpdi driver

- qcom,cpuss-debug-cgc: debug clock gating phandle for etm

	reg : the clock gating register for each cluster

	cluster : indicate the cluster number

coresight-outports, coresight-child-list and coresight-child-ports lists will

be of the same length and will have a one to one correspondence among the

elements at the same list index.

coresight-default-sink must be specified for one of the sink devices that is

intended to be made the default sink. Other sink devices must not have this

specified. Not specifying this property on any of the sinks is invalid.

specification and can be connected in various topologies to suit a particular

SoCs tracing needs. These trace components can generally be classified as

sinks, links and sources. Trace data produced by one or more sources flows

through the intermediate links connecting the source to the currently selected

sink. Each CoreSight component device should use these properties to describe

its hardware characteristcs.

* Required properties for all components *except* non-configurable replicators:

* LPM Workarounds

The required properties are:

- compatible: "qcom,lpm-workarounds"

The optional properties are:

- reg: The physical address and the size of the l1_l2_gcc and l2_pwr_sts

	regitsters of performance cluster.

- reg-names: "l2_pwr_sts" - string to identify l2_pwr_sts physical address.

	     "l1_l2_gcc" - string to identify l1_l2_gcc physical address.

- qcom,lpm-wa-cx-turbo-unvote: Indicates the workaround to unvote CX turbo

	vote when system is coming out of rpm assisted power collaspe.

	lpm-cx-supply is required if this is present.

- lpm-cx-supply:  will hold handle for CX regulator supply which is used

	to unvote.

- qcom,lpm-wa-skip-l2-spm: Due to a hardware bug on 8939 and 8909, secure

	world needs to disable and enable L2 SPM to get the proper context

	in secure watchdog bite cases. With this workaround there is a race

	in programming L2 SPM between HLOS and secure world. This leads to

	stability issues. To avoid this program L2 SPM only in secure world

	based on the L2 mode flag passed. Set lpm-wa-skip-l2-spm node if this

	is required.

- qcom,lpm-wa-dynamic-clock-gating: Due to a hardware bug on 8952, L1/L2 dynamic

	clock gating needs to be enabled by software for performance cluster

	cores and L2. Set lpm-wa-dynamic-clock-gating node if this workaround is

	required.

- qcom,cpu-offline-mask: Dynamic clock gating should be enabled when cluster is

	in L2 PC. Each bit of cpu-offline-mask lists the cpu no. to hotplug by KTM

	driver.

- qcom,non-boot-cpu-index: will hold index of non boot cluster cpu.

- qcom,l1-l2-gcc-secure: indicates L1/L2 clock enabling register is secure.

Example:

qcom,lpm-workarounds {

	compatible = "qcom,lpm-workarounds";

	reg = <0x0B011018 0x4>,

	      <0x0B011088 0x4>;

	reg-names = "l2-pwr-sts", "l1-l2-gcc";

	lpm-cx-supply = <&pm8916_s2_corner>;

	qcom,lpm-wa-cx-turbo-unvote;

	qcom,lpm-wa-skip-l2-spm;

	qcom,lpm-wa-dynamic-clock-gating;

	qcom,cpu-offline-mask = "0xF";

	qcom,non-boot-cpu-index = <4>;

}

* MCD (MobiCore Driver)

t-base is an operating system running in the secure world (TrustZone).

The t-base implementation consists of several components in the

secure world and the non-secure world (kernel and user space). The

MobiCore driver communicates with the t-base operating system that

exists in TrustZone.

Required properties:

  - compatible: Should be "qcom,mcd"

  - qcom,ce-hw-instance: should contain crypto HW instance

  - qcom,ce-device: Device number

  - clocks: Array of <clock_controller_phandle clock_reference> listing

            all the clocks that are accesed by this subsystem.

  - qcom,ce-opp-freq: indicates the CE operating frequency in Hz, changes from target to target.

Example:

	mcd {

		compatible = "qcom,mcd";

		qcom,ce-hw-instance = <0>;

		qcom,ce-device = <0>;

		clocks = <&clock_gcc clk_crypto_clk_src>,

			 <&clock_gcc clk_gcc_crypto_clk>,

			 <&clock_gcc clk_gcc_crypto_ahb_clk>,

			 <&clock_gcc clk_gcc_crypto_axi_clk>;

		clock-names = "core_clk_src", "core_clk",

				"iface_clk", "bus_clk";

		qcom,ce-opp-freq = <100000000>;

	};