Loading arch/arm/boot/dts/qcom/sdxpoorwills.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -936,7 +936,7 @@ qcom,ipa-hw-mode = <0>; qcom,ee = <0>; qcom,use-ipa-tethering-bridge; qcom,mhi-event-ring-id-limits = <9 10>; /* start and end */ qcom,mhi-event-ring-id-limits = <9 11>; /* start and end */ qcom,modem-cfg-emb-pipe-flt; qcom,use-ipa-pm; qcom,wlan-ce-db-over-pcie; Loading drivers/platform/msm/ipa/ipa_api.c +5 −0 Original line number Diff line number Diff line Loading @@ -182,7 +182,12 @@ const char *ipa_clients_strings[IPA_CLIENT_MAX] = { __stringify(IPA_CLIENT_TEST3_CONS), __stringify(IPA_CLIENT_TEST4_PROD), __stringify(IPA_CLIENT_TEST4_CONS), __stringify(RESERVERD_PROD_72), __stringify(IPA_CLIENT_DUMMY_CONS), __stringify(RESERVERD_PROD_74), __stringify(IPA_CLIENT_MHI_DPL_CONS), __stringify(RESERVERD_PROD_76), __stringify(IPA_CLIENT_DUMMY_CONS1) }; /** Loading drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c +1 −1 Original line number Diff line number Diff line Loading @@ -67,7 +67,7 @@ #define IPA_MHI_SUSPEND_SLEEP_MAX 1100 #define IPA_MHI_MAX_UL_CHANNELS 1 #define IPA_MHI_MAX_DL_CHANNELS 1 #define IPA_MHI_MAX_DL_CHANNELS 2 /* bit #40 in address should be asserted for MHI transfers over pcie */ #define IPA_MHI_CLIENT_HOST_ADDR_COND(addr) \ Loading drivers/platform/msm/ipa/ipa_v3/ipa_client.c +2 −1 Original line number Diff line number Diff line Loading @@ -68,7 +68,8 @@ int ipa3_enable_data_path(u32 clnt_hdl) * if DPL client is not pulling the data * on other end from IPA hw. */ if (ep->client == IPA_CLIENT_USB_DPL_CONS) if ((ep->client == IPA_CLIENT_USB_DPL_CONS) || (ep->client == IPA_CLIENT_MHI_DPL_CONS)) holb_cfg.en = IPA_HOLB_TMR_EN; else holb_cfg.en = IPA_HOLB_TMR_DIS; Loading drivers/platform/msm/ipa/ipa_v3/ipa_mhi.c +5 −3 Original line number Diff line number Diff line Loading @@ -61,7 +61,7 @@ IPA_MHI_DBG("EXIT\n") #define IPA_MHI_MAX_UL_CHANNELS 1 #define IPA_MHI_MAX_DL_CHANNELS 1 #define IPA_MHI_MAX_DL_CHANNELS 2 /* bit #40 in address should be asserted for MHI transfers over pcie */ #define IPA_MHI_HOST_ADDR_COND(addr) \ Loading Loading @@ -283,8 +283,10 @@ static int ipa_mhi_start_gsi_channel(enum ipa_client_type client, ch_props.ring_base_addr = IPA_MHI_HOST_ADDR_COND( params->ch_ctx_host->rbase); if (params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_DEFAULT || params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_ENABLE) { /* Burst mode is not supported on DPL pipes */ if ((client != IPA_CLIENT_MHI_DPL_CONS) && (params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_DEFAULT || params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_ENABLE)) { burst_mode_enabled = true; } Loading Loading
arch/arm/boot/dts/qcom/sdxpoorwills.dtsi +1 −1 Original line number Diff line number Diff line Loading @@ -936,7 +936,7 @@ qcom,ipa-hw-mode = <0>; qcom,ee = <0>; qcom,use-ipa-tethering-bridge; qcom,mhi-event-ring-id-limits = <9 10>; /* start and end */ qcom,mhi-event-ring-id-limits = <9 11>; /* start and end */ qcom,modem-cfg-emb-pipe-flt; qcom,use-ipa-pm; qcom,wlan-ce-db-over-pcie; Loading
drivers/platform/msm/ipa/ipa_api.c +5 −0 Original line number Diff line number Diff line Loading @@ -182,7 +182,12 @@ const char *ipa_clients_strings[IPA_CLIENT_MAX] = { __stringify(IPA_CLIENT_TEST3_CONS), __stringify(IPA_CLIENT_TEST4_PROD), __stringify(IPA_CLIENT_TEST4_CONS), __stringify(RESERVERD_PROD_72), __stringify(IPA_CLIENT_DUMMY_CONS), __stringify(RESERVERD_PROD_74), __stringify(IPA_CLIENT_MHI_DPL_CONS), __stringify(RESERVERD_PROD_76), __stringify(IPA_CLIENT_DUMMY_CONS1) }; /** Loading
drivers/platform/msm/ipa/ipa_clients/ipa_mhi_client.c +1 −1 Original line number Diff line number Diff line Loading @@ -67,7 +67,7 @@ #define IPA_MHI_SUSPEND_SLEEP_MAX 1100 #define IPA_MHI_MAX_UL_CHANNELS 1 #define IPA_MHI_MAX_DL_CHANNELS 1 #define IPA_MHI_MAX_DL_CHANNELS 2 /* bit #40 in address should be asserted for MHI transfers over pcie */ #define IPA_MHI_CLIENT_HOST_ADDR_COND(addr) \ Loading
drivers/platform/msm/ipa/ipa_v3/ipa_client.c +2 −1 Original line number Diff line number Diff line Loading @@ -68,7 +68,8 @@ int ipa3_enable_data_path(u32 clnt_hdl) * if DPL client is not pulling the data * on other end from IPA hw. */ if (ep->client == IPA_CLIENT_USB_DPL_CONS) if ((ep->client == IPA_CLIENT_USB_DPL_CONS) || (ep->client == IPA_CLIENT_MHI_DPL_CONS)) holb_cfg.en = IPA_HOLB_TMR_EN; else holb_cfg.en = IPA_HOLB_TMR_DIS; Loading
drivers/platform/msm/ipa/ipa_v3/ipa_mhi.c +5 −3 Original line number Diff line number Diff line Loading @@ -61,7 +61,7 @@ IPA_MHI_DBG("EXIT\n") #define IPA_MHI_MAX_UL_CHANNELS 1 #define IPA_MHI_MAX_DL_CHANNELS 1 #define IPA_MHI_MAX_DL_CHANNELS 2 /* bit #40 in address should be asserted for MHI transfers over pcie */ #define IPA_MHI_HOST_ADDR_COND(addr) \ Loading Loading @@ -283,8 +283,10 @@ static int ipa_mhi_start_gsi_channel(enum ipa_client_type client, ch_props.ring_base_addr = IPA_MHI_HOST_ADDR_COND( params->ch_ctx_host->rbase); if (params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_DEFAULT || params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_ENABLE) { /* Burst mode is not supported on DPL pipes */ if ((client != IPA_CLIENT_MHI_DPL_CONS) && (params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_DEFAULT || params->ch_ctx_host->brstmode == IPA_MHI_BURST_MODE_ENABLE)) { burst_mode_enabled = true; } Loading