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Commit 58035fcc authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'renesas-soc-for-v3.15' of... 

Merge tag 'renesas-soc-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers

Merge "Renesas ARM Based SoC Updates for v3.15" from Simon Horman:

* r7s72100 SoC (RZ/A1H)
  - Add i2c clocks (portion missing from previous patch due to miss-merge)

* r8a7791 (R-Car M2)
  - Add SATA clocks
  - Add ZS clock
  - Wait for status on all MSTP clocks
 -- Add I2C and VIN clocks

* r8a7790 (R-Car H2)
  - Add PCI USB host clock support
  - Add Audio DMAC, SATA and VIN clocks
  - Add Audio DMAC support

* r8a7779 (R-Car H1)
  - Wait for status on selected MSTP clocks

* tag 'renesas-soc-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: r8a7790: Add PCI USB host clock support
  ARM: shmobile: r7s72100: really add i2c clocks
  ARM: shmobile: r8a7791: Add SATA clocks
  ARM: shmobile: r8a7791: Add ZS clock
  ARM: shmobile: r8a7790: Add SATA clocks
  ARM: shmobile: r8a7790: Add VIN clock support
  ARM: shmobile: r8a7790: add Audio DMAC support
  ARM: shmobile: r8a7790: add Audio DMAC clock
  ARM: shmobile: r8a7791: Wait for status on all MSTP clocks
  ARM: shmobile: r8a7791: Add VIN clocks
  ARM: shmobile: r8a7791: Add I2C clocks
  ARM: shmobile: r8a7790: Wait for status on all MSTP clocks
  ARM: shmobile: r8a7779: Wait for status on selected MSTP clocks
  ARM: shmobile: wait for MSTP clock status to toggle, when enabling it
parents 805937cf 012a7069

arch/arm/mach-shmobile/clock-r7s72100.c

+4 −0
Original line number Diff line number Diff line
@@ -176,6 +176,10 @@ static struct clk_lookup lookups[] = { 
	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),



	/* MSTP clocks */

	CLKDEV_DEV_ID("fcfee000.i2c", &mstp_clks[MSTP97]),

	CLKDEV_DEV_ID("fcfee400.i2c", &mstp_clks[MSTP96]),

	CLKDEV_DEV_ID("fcfee800.i2c", &mstp_clks[MSTP95]),

	CLKDEV_DEV_ID("fcfeec00.i2c", &mstp_clks[MSTP94]),

	CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP33]),



	/* ICK */

arch/arm/mach-shmobile/clock-r8a7779.c

+10 −10
Original line number Diff line number Diff line
@@ -127,16 +127,16 @@ static struct clk mstp_clks[MSTP_NR] = { 
	[MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */

	[MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */

	[MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */

	[MSTP120] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 20, 0), /* VIN3 */

	[MSTP116] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 16, 0), /* PCIe */

	[MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */

	[MSTP114] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 14, 0), /* Ether */

	[MSTP110] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 10, 0), /* VIN0 */

	[MSTP109] = SH_CLK_MSTP32(&clks_clk, MSTPCR1,  9, 0), /* VIN1 */

	[MSTP108] = SH_CLK_MSTP32(&clks_clk, MSTPCR1,  8, 0), /* VIN2 */

	[MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1,  3, 0), /* DU */

	[MSTP101] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1,  1, 0), /* USB2 */

	[MSTP100] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1,  0, 0), /* USB0/1 */

	[MSTP120] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 20, MSTPSR1, 0), /* VIN3 */

	[MSTP116] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 16, MSTPSR1, 0), /* PCIe */

	[MSTP115] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 15, MSTPSR1, 0), /* SATA */

	[MSTP114] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1, 14, MSTPSR1, 0), /* Ether */

	[MSTP110] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1, 10, MSTPSR1, 0), /* VIN0 */

	[MSTP109] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1,  9, MSTPSR1, 0), /* VIN1 */

	[MSTP108] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1,  8, MSTPSR1, 0), /* VIN2 */

	[MSTP103] = SH_CLK_MSTP32_STS(&clks_clk, MSTPCR1,  3, MSTPSR1, 0), /* DU */

	[MSTP101] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1,  1, MSTPSR1, 0), /* USB2 */

	[MSTP100] = SH_CLK_MSTP32_STS(&clkp_clk, MSTPCR1,  0, MSTPSR1, 0), /* USB0/1 */

	[MSTP030] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 30, 0), /* I2C0 */

	[MSTP029] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 29, 0), /* I2C1 */

	[MSTP028] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 28, 0), /* I2C2 */

arch/arm/mach-shmobile/clock-r8a7790.c

+86 −54
Original line number Diff line number Diff line
@@ -55,6 +55,15 @@ 
#define SMSTPCR9	0xe6150994

#define SMSTPCR10	0xe6150998



#define MSTPSR1		IOMEM(0xe6150038)

#define MSTPSR2		IOMEM(0xe6150040)

#define MSTPSR3		IOMEM(0xe6150048)

#define MSTPSR5		IOMEM(0xe615003c)

#define MSTPSR7		IOMEM(0xe61501c4)

#define MSTPSR8		IOMEM(0xe61509a0)

#define MSTPSR9		IOMEM(0xe61509a4)

#define MSTPSR10	IOMEM(0xe61509a8)



#define SDCKCR		0xE6150074

#define SD2CKCR		0xE6150078

#define SD3CKCR		0xE615007C
@@ -187,11 +196,14 @@ enum { 
	MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,

	MSTP931, MSTP930, MSTP929, MSTP928,

	MSTP917,

	MSTP815, MSTP814,

	MSTP813,

	MSTP811, MSTP810, MSTP809, MSTP808,

	MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,

	MSTP717, MSTP716,

	MSTP704,

	MSTP704, MSTP703,

	MSTP522,

	MSTP502, MSTP501,

	MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,

	MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,

	MSTP124,
@@ -199,48 +211,57 @@ enum { 
};



static struct clk mstp_clks[MSTP_NR] = {

	[MSTP1015] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 15, 0), /* SSI0 */

	[MSTP1014] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 14, 0), /* SSI1 */

	[MSTP1013] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 13, 0), /* SSI2 */

	[MSTP1012] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 12, 0), /* SSI3 */

	[MSTP1011] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 11, 0), /* SSI4 */

	[MSTP1010] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 10, 0), /* SSI5 */

	[MSTP1009] = SH_CLK_MSTP32(&p_clk, SMSTPCR10,  9, 0), /* SSI6 */

	[MSTP1008] = SH_CLK_MSTP32(&p_clk, SMSTPCR10,  8, 0), /* SSI7 */

	[MSTP1007] = SH_CLK_MSTP32(&p_clk, SMSTPCR10,  7, 0), /* SSI8 */

	[MSTP1006] = SH_CLK_MSTP32(&p_clk, SMSTPCR10,  6, 0), /* SSI9 */

	[MSTP1005] = SH_CLK_MSTP32(&p_clk, SMSTPCR10,  5, 0), /* SSI ALL */

	[MSTP931] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 31, 0), /* I2C0 */

	[MSTP930] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 30, 0), /* I2C1 */

	[MSTP929] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 29, 0), /* I2C2 */

	[MSTP928] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 28, 0), /* I2C3 */

	[MSTP917] = SH_CLK_MSTP32(&qspi_clk, SMSTPCR9, 17, 0), /* QSPI */

	[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */

	[MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */

	[MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */

	[MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */

	[MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */

	[MSTP722] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 22, 0), /* DU2 */

	[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */

	[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */

	[MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */

	[MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */

	[MSTP704] = SH_CLK_MSTP32(&mp_clk, SMSTPCR7, 4, 0), /* HSUSB */

	[MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */

	[MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */

	[MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */

	[MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_SD1], SMSTPCR3, 13, 0), /* SDHI1 */

	[MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SD2], SMSTPCR3, 12, 0), /* SDHI2 */

	[MSTP311] = SH_CLK_MSTP32(&div6_clks[DIV6_SD3], SMSTPCR3, 11, 0), /* SDHI3 */

	[MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, 0), /* MMC1 */

	[MSTP304] = SH_CLK_MSTP32(&cp_clk, SMSTPCR3, 4, 0), /* TPU0 */

	[MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */

	[MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */

	[MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */

	[MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */

	[MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */

	[MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */

	[MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */

	[MSTP1015] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 15, MSTPSR10, 0), /* SSI0 */

	[MSTP1014] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 14, MSTPSR10, 0), /* SSI1 */

	[MSTP1013] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 13, MSTPSR10, 0), /* SSI2 */

	[MSTP1012] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 12, MSTPSR10, 0), /* SSI3 */

	[MSTP1011] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 11, MSTPSR10, 0), /* SSI4 */

	[MSTP1010] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 10, MSTPSR10, 0), /* SSI5 */

	[MSTP1009] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 9, MSTPSR10, 0), /* SSI6 */

	[MSTP1008] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 8, MSTPSR10, 0), /* SSI7 */

	[MSTP1007] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 7, MSTPSR10, 0), /* SSI8 */

	[MSTP1006] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 6, MSTPSR10, 0), /* SSI9 */

	[MSTP1005] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 5, MSTPSR10, 0), /* SSI ALL */

	[MSTP931] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */

	[MSTP930] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */

	[MSTP929] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */

	[MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */

	[MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */

	[MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */

	[MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */

	[MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */

	[MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */

	[MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */

	[MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8,  9, MSTPSR8, 0), /* VIN2 */

	[MSTP808] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8,  8, MSTPSR8, 0), /* VIN3 */

	[MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */

	[MSTP725] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 25, MSTPSR7, 0), /* LVDS1 */

	[MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */

	[MSTP723] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 23, MSTPSR7, 0), /* DU1 */

	[MSTP722] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 22, MSTPSR7, 0), /* DU2 */

	[MSTP721] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 21, MSTPSR7, 0), /* SCIF0 */

	[MSTP720] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 20, MSTPSR7, 0), /* SCIF1 */

	[MSTP717] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 17, MSTPSR7, 0), /* HSCIF0 */

	[MSTP716] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 16, MSTPSR7, 0), /* HSCIF1 */

	[MSTP704] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 4, MSTPSR7, 0), /* HSUSB */

	[MSTP703] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 3, MSTPSR7, 0), /* EHCI */

	[MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */

	[MSTP502] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 2, MSTPSR5, 0), /* Audio-DMAC low */

	[MSTP501] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 1, MSTPSR5, 0), /* Audio-DMAC hi */

	[MSTP315] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, MSTPSR3, 0), /* MMC0 */

	[MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */

	[MSTP313] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD1], SMSTPCR3, 13, MSTPSR3, 0), /* SDHI1 */

	[MSTP312] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD2], SMSTPCR3, 12, MSTPSR3, 0), /* SDHI2 */

	[MSTP311] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD3], SMSTPCR3, 11, MSTPSR3, 0), /* SDHI3 */

	[MSTP305] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, MSTPSR3, 0), /* MMC1 */

	[MSTP304] = SH_CLK_MSTP32_STS(&cp_clk, SMSTPCR3, 4, MSTPSR3, 0), /* TPU0 */

	[MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */

	[MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */

	[MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */

	[MSTP204] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 4, MSTPSR2, 0), /* SCIFA0 */

	[MSTP203] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 3, MSTPSR2, 0), /* SCIFA1 */

	[MSTP202] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 2, MSTPSR2, 0), /* SCIFA2 */

	[MSTP124] = SH_CLK_MSTP32_STS(&rclk_clk, SMSTPCR1, 24, MSTPSR1, 0), /* CMT0 */

};



static struct clk_lookup lookups[] = {
@@ -300,8 +321,14 @@ static struct clk_lookup lookups[] = { 
	CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),

	CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),

	CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),

	CLKDEV_DEV_ID("r8a7790-vin.0", &mstp_clks[MSTP811]),

	CLKDEV_DEV_ID("r8a7790-vin.1", &mstp_clks[MSTP810]),

	CLKDEV_DEV_ID("r8a7790-vin.2", &mstp_clks[MSTP809]),

	CLKDEV_DEV_ID("r8a7790-vin.3", &mstp_clks[MSTP808]),

	CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),

	CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),

	CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP502]),

	CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP501]),

	CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]),

	CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),

	CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]),
@@ -317,6 +344,11 @@ static struct clk_lookup lookups[] = { 
	CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),

	CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),

	CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),

	CLKDEV_DEV_ID("pci-rcar-gen2.0", &mstp_clks[MSTP703]),

	CLKDEV_DEV_ID("pci-rcar-gen2.1", &mstp_clks[MSTP703]),

	CLKDEV_DEV_ID("pci-rcar-gen2.2", &mstp_clks[MSTP703]),

	CLKDEV_DEV_ID("sata-r8a7790.0", &mstp_clks[MSTP815]),

	CLKDEV_DEV_ID("sata-r8a7790.1", &mstp_clks[MSTP814]),



	/* ICK */

	CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),

arch/arm/mach-shmobile/clock-r8a7791.c

+60 −21
Original line number Diff line number Diff line
@@ -59,6 +59,14 @@ 
#define SMSTPCR10	0xE6150998

#define SMSTPCR11	0xE615099C



#define MSTPSR1		IOMEM(0xe6150038)

#define MSTPSR2		IOMEM(0xe6150040)

#define MSTPSR5		IOMEM(0xe615003c)

#define MSTPSR7		IOMEM(0xe61501c4)

#define MSTPSR8		IOMEM(0xe61509a0)

#define MSTPSR9		IOMEM(0xe61509a4)

#define MSTPSR11	IOMEM(0xe61509ac)



#define MODEMR		0xE6160060

#define SDCKCR		0xE6150074

#define SD2CKCR		0xE6150078
@@ -103,7 +111,9 @@ SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12); 
SH_FIXED_RATIO_CLK_SET(p_clk,			pll1_clk,	1, 24);

SH_FIXED_RATIO_CLK_SET(rclk_clk,		pll1_clk,	1, (48 * 1024));

SH_FIXED_RATIO_CLK_SET(mp_clk,			pll1_div2_clk,	1, 15);

SH_FIXED_RATIO_CLK_SET(zg_clk,			pll1_clk,	1, 3);

SH_FIXED_RATIO_CLK_SET(zx_clk,			pll1_clk,	1, 3);

SH_FIXED_RATIO_CLK_SET(zs_clk,			pll1_clk,	1, 6);



static struct clk *main_clks[] = {

	&extal_clk,
@@ -117,12 +127,17 @@ static struct clk *main_clks[] = { 
	&rclk_clk,

	&mp_clk,

	&cp_clk,

	&zg_clk,

	&zx_clk,

	&zs_clk,

};



/* MSTP */

enum {

	MSTP931, MSTP930, MSTP929, MSTP928, MSTP927, MSTP925,

	MSTP815, MSTP814,

	MSTP813,

	MSTP811, MSTP810, MSTP809,

	MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,

	MSTP719, MSTP718, MSTP715, MSTP714,

	MSTP522,
@@ -133,27 +148,38 @@ enum { 
};



static struct clk mstp_clks[MSTP_NR] = {

	[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */

	[MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */

	[MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */

	[MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */

	[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */

	[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */

	[MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */

	[MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */

	[MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */

	[MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */

	[MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */

	[MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */

	[MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */

	[MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */

	[MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */

	[MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */

	[MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */

	[MSTP1105] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 5, 0), /* SCIFA3 */

	[MSTP1106] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 6, 0), /* SCIFA4 */

	[MSTP1107] = SH_CLK_MSTP32(&mp_clk, SMSTPCR11, 7, 0), /* SCIFA5 */

	[MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */

	[MSTP931] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */

	[MSTP930] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */

	[MSTP929] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */

	[MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */

	[MSTP927] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4 */

	[MSTP925] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5 */

	[MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */

	[MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */

	[MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */

	[MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */

	[MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */

	[MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 9, MSTPSR8, 0), /* VIN2 */

	[MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */

	[MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */

	[MSTP723] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 23, MSTPSR7, 0), /* DU1 */

	[MSTP721] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 21, MSTPSR7, 0), /* SCIF0 */

	[MSTP720] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 20, MSTPSR7, 0), /* SCIF1 */

	[MSTP719] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 19, MSTPSR7, 0), /* SCIF2 */

	[MSTP718] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 18, MSTPSR7, 0), /* SCIF3 */

	[MSTP715] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 15, MSTPSR7, 0), /* SCIF4 */

	[MSTP714] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 14, MSTPSR7, 0), /* SCIF5 */

	[MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */

	[MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */

	[MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */

	[MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */

	[MSTP204] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 4, MSTPSR2, 0), /* SCIFA0 */

	[MSTP203] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 3, MSTPSR2, 0), /* SCIFA1 */

	[MSTP202] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 2, MSTPSR2, 0), /* SCIFA2 */

	[MSTP1105] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 5, MSTPSR11, 0), /* SCIFA3 */

	[MSTP1106] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 6, MSTPSR11, 0), /* SCIFA4 */

	[MSTP1107] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 7, MSTPSR11, 0), /* SCIFA5 */

	[MSTP124] = SH_CLK_MSTP32_STS(&rclk_clk, SMSTPCR1, 24, MSTPSR1, 0), /* CMT0 */

};



static struct clk_lookup lookups[] = {
@@ -165,6 +191,8 @@ static struct clk_lookup lookups[] = { 
	CLKDEV_CON_ID("pll1",		&pll1_clk),

	CLKDEV_CON_ID("pll1_div2",	&pll1_div2_clk),

	CLKDEV_CON_ID("pll3",		&pll3_clk),

	CLKDEV_CON_ID("zg",		&zg_clk),

	CLKDEV_CON_ID("zs",		&zs_clk),

	CLKDEV_CON_ID("hp",		&hp_clk),

	CLKDEV_CON_ID("p",		&p_clk),

	CLKDEV_CON_ID("rclk",		&rclk_clk),
@@ -194,7 +222,18 @@ static struct clk_lookup lookups[] = { 
	CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),

	CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),

	CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),

	CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),

	CLKDEV_DEV_ID("i2c-rcar_gen2.1", &mstp_clks[MSTP930]),

	CLKDEV_DEV_ID("i2c-rcar_gen2.2", &mstp_clks[MSTP929]),

	CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),

	CLKDEV_DEV_ID("i2c-rcar_gen2.4", &mstp_clks[MSTP927]),

	CLKDEV_DEV_ID("i2c-rcar_gen2.5", &mstp_clks[MSTP925]),

	CLKDEV_DEV_ID("r8a7791-ether", &mstp_clks[MSTP813]), /* Ether */

	CLKDEV_DEV_ID("r8a7791-vin.0", &mstp_clks[MSTP811]),

	CLKDEV_DEV_ID("r8a7791-vin.1", &mstp_clks[MSTP810]),

	CLKDEV_DEV_ID("r8a7791-vin.2", &mstp_clks[MSTP809]),

	CLKDEV_DEV_ID("sata-r8a7791.0", &mstp_clks[MSTP815]),

	CLKDEV_DEV_ID("sata-r8a7791.1", &mstp_clks[MSTP814]),

};



#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31)		\

arch/arm/mach-shmobile/include/mach/r8a7790.h

+25 −0
Original line number Diff line number Diff line
@@ -3,6 +3,31 @@ 


#include <mach/rcar-gen2.h>



/* DMA slave IDs */

enum {

	RCAR_DMA_SLAVE_INVALID,

	AUDIO_DMAC_SLAVE_SSI0_TX,

	AUDIO_DMAC_SLAVE_SSI0_RX,

	AUDIO_DMAC_SLAVE_SSI1_TX,

	AUDIO_DMAC_SLAVE_SSI1_RX,

	AUDIO_DMAC_SLAVE_SSI2_TX,

	AUDIO_DMAC_SLAVE_SSI2_RX,

	AUDIO_DMAC_SLAVE_SSI3_TX,

	AUDIO_DMAC_SLAVE_SSI3_RX,

	AUDIO_DMAC_SLAVE_SSI4_TX,

	AUDIO_DMAC_SLAVE_SSI4_RX,

	AUDIO_DMAC_SLAVE_SSI5_TX,

	AUDIO_DMAC_SLAVE_SSI5_RX,

	AUDIO_DMAC_SLAVE_SSI6_TX,

	AUDIO_DMAC_SLAVE_SSI6_RX,

	AUDIO_DMAC_SLAVE_SSI7_TX,

	AUDIO_DMAC_SLAVE_SSI7_RX,

	AUDIO_DMAC_SLAVE_SSI8_TX,

	AUDIO_DMAC_SLAVE_SSI8_RX,

	AUDIO_DMAC_SLAVE_SSI9_TX,

	AUDIO_DMAC_SLAVE_SSI9_RX,

};



void r8a7790_add_standard_devices(void);

void r8a7790_add_dt_devices(void);

void r8a7790_clock_init(void);