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Commit 5762a179 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-intel-next' of... 

Merge branch 'drm-intel-next' of ssh://master.kernel.org/pub/scm/linux/kernel/git/keithp/linux-2.6 into drm-core-next

* 'drm-intel-next' of ssh://master.kernel.org/pub/scm/linux/kernel/git/keithp/linux-2.6: (52 commits)
  drm/i915: provide module parameter description
  drm/i915: add module parameter compiler hints
  drm/i915/bios: Avoid temporary allocation whilst searching for downclock
  drm/i915: Cache GT fifo count for SandyBridge
  i915: Fix opregion notifications
  drm/i915: TVDAC_STATE_CHG does not indicate successful load-detect
  drm/i915: Select correct pipe during TV detect
  drm/i915/ringbuffer: Idling requires waiting for the ring to be empty
  Revert "drm/i915: enable rc6 by default"
  drm/i915: Clean up i915_driver_load failure path
  drm/i915: Enable i915 frame buffer compression by default
  drm/i915: Share the common work of disabling active FBC before updating
  drm/i915: Perform intel_enable_fbc() from a delayed task
  drm/i915: Disable FBC across page-flipping
  drm/i915: Set persistent-mode for ILK/SNB framebuffer compression
  drm/i915: Use of a CPU fence is mandatory to update FBC regions upon CPU writes
  drm/i915: Remove vestigial pitch from post-gen2 FBC control routines
  drm/i915: Replace direct calls to vfunc.disable_fbc with intel_disable_fbc()
  drm/i915: Only export the generic intel_disable_fbc() interface
  drm/i915: Enable GPU reset on Ivybridge.
  ...
parents cf056edb 6e96e775

drivers/acpi/video.c

+4 −3
Original line number Diff line number Diff line
@@ -46,7 +46,6 @@ 


#define PREFIX "ACPI: "



#define ACPI_VIDEO_CLASS		"video"

#define ACPI_VIDEO_BUS_NAME		"Video Bus"

#define ACPI_VIDEO_DEVICE_NAME		"Video Device"

#define ACPI_VIDEO_NOTIFY_SWITCH	0x80
@@ -1445,6 +1444,7 @@ static void acpi_video_bus_notify(struct acpi_device *device, u32 event) 
	case ACPI_VIDEO_NOTIFY_SWITCH:	/* User requested a switch,

					 * most likely via hotkey. */

		acpi_bus_generate_proc_event(device, event, 0);

		if (!acpi_notifier_call_chain(device, event, 0))

			keycode = KEY_SWITCHVIDEOMODE;

		break;
@@ -1475,6 +1475,7 @@ static void acpi_video_bus_notify(struct acpi_device *device, u32 event) 
		break;

	}



	if (event != ACPI_VIDEO_NOTIFY_SWITCH)

		acpi_notifier_call_chain(device, event, 0);



	if (keycode) {

drivers/cpufreq/cpufreq.c

+20 −0
Original line number Diff line number Diff line
@@ -1199,6 +1199,26 @@ unsigned int cpufreq_quick_get(unsigned int cpu) 
}

EXPORT_SYMBOL(cpufreq_quick_get);



/**

 * cpufreq_quick_get_max - get the max reported CPU frequency for this CPU

 * @cpu: CPU number

 *

 * Just return the max possible frequency for a given CPU.

 */

unsigned int cpufreq_quick_get_max(unsigned int cpu)

{

	struct cpufreq_policy *policy = cpufreq_cpu_get(cpu);

	unsigned int ret_freq = 0;



	if (policy) {

		ret_freq = policy->max;

		cpufreq_cpu_put(policy);

	}



	return ret_freq;

}

EXPORT_SYMBOL(cpufreq_quick_get_max);





static unsigned int __cpufreq_get(unsigned int cpu)

{

drivers/gpu/drm/drm_crtc_helper.c

+5 −0
Original line number Diff line number Diff line
@@ -560,6 +560,11 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) 
			mode_changed = true;

		} else if (set->fb == NULL) {

			mode_changed = true;

		} else if (set->fb->depth != set->crtc->fb->depth) {

			mode_changed = true;

		} else if (set->fb->bits_per_pixel !=

			   set->crtc->fb->bits_per_pixel) {

			mode_changed = true;

		} else

			fb_changed = true;

	}

drivers/gpu/drm/i915/i915_debugfs.c

+40 −1
Original line number Diff line number Diff line
@@ -865,7 +865,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused) 
			   MEMSTAT_VID_SHIFT);

		seq_printf(m, "Current P-state: %d\n",

			   (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);

	} else if (IS_GEN6(dev)) {

	} else if (IS_GEN6(dev) || IS_GEN7(dev)) {

		u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);

		u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);

		u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
@@ -1123,6 +1123,44 @@ static int i915_emon_status(struct seq_file *m, void *unused) 
	return 0;

}



static int i915_ring_freq_table(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = (struct drm_info_node *) m->private;

	struct drm_device *dev = node->minor->dev;

	drm_i915_private_t *dev_priv = dev->dev_private;

	int ret;

	int gpu_freq, ia_freq;



	if (!(IS_GEN6(dev) || IS_GEN7(dev))) {

		seq_printf(m, "unsupported on this chipset\n");

		return 0;

	}



	ret = mutex_lock_interruptible(&dev->struct_mutex);

	if (ret)

		return ret;



	seq_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");



	for (gpu_freq = dev_priv->min_delay; gpu_freq <= dev_priv->max_delay;

	     gpu_freq++) {

		I915_WRITE(GEN6_PCODE_DATA, gpu_freq);

		I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |

			   GEN6_PCODE_READ_MIN_FREQ_TABLE);

		if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &

			      GEN6_PCODE_READY) == 0, 10)) {

			DRM_ERROR("pcode read of freq table timed out\n");

			continue;

		}

		ia_freq = I915_READ(GEN6_PCODE_DATA);

		seq_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100);

	}



	mutex_unlock(&dev->struct_mutex);



	return 0;

}



static int i915_gfxec(struct seq_file *m, void *unused)

{

	struct drm_info_node *node = (struct drm_info_node *) m->private;
@@ -1430,6 +1468,7 @@ static struct drm_info_list i915_debugfs_list[] = { 
	{"i915_inttoext_table", i915_inttoext_table, 0},

	{"i915_drpc_info", i915_drpc_info, 0},

	{"i915_emon_status", i915_emon_status, 0},

	{"i915_ring_freq_table", i915_ring_freq_table, 0},

	{"i915_gfxec", i915_gfxec, 0},

	{"i915_fbc_status", i915_fbc_status, 0},

	{"i915_sr_status", i915_sr_status, 0},

drivers/gpu/drm/i915/i915_dma.c

+14 −4
Original line number Diff line number Diff line
@@ -1073,6 +1073,9 @@ static void i915_setup_compression(struct drm_device *dev, int size) 
	unsigned long cfb_base;

	unsigned long ll_base = 0;



	/* Just in case the BIOS is doing something questionable. */

	intel_disable_fbc(dev);



	compressed_fb = drm_mm_search_free(&dev_priv->mm.stolen, size, 4096, 0);

	if (compressed_fb)

		compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
@@ -1099,7 +1102,6 @@ static void i915_setup_compression(struct drm_device *dev, int size) 


	dev_priv->cfb_size = size;



	intel_disable_fbc(dev);

	dev_priv->compressed_fb = compressed_fb;

	if (HAS_PCH_SPLIT(dev))

		I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
@@ -1943,7 +1945,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
	if (!dev_priv->mm.gtt) {

		DRM_ERROR("Failed to initialize GTT\n");

		ret = -ENODEV;

		goto out_iomapfree;

		goto out_rmmap;

	}



	agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
@@ -1987,7 +1989,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
	if (dev_priv->wq == NULL) {

		DRM_ERROR("Failed to create our workqueue.\n");

		ret = -ENOMEM;

		goto out_iomapfree;

		goto out_mtrrfree;

	}



	/* enable GEM by default */
@@ -2074,13 +2076,21 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
	return 0;



out_gem_unload:

	if (dev_priv->mm.inactive_shrinker.shrink)

		unregister_shrinker(&dev_priv->mm.inactive_shrinker);



	if (dev->pdev->msi_enabled)

		pci_disable_msi(dev->pdev);



	intel_teardown_gmbus(dev);

	intel_teardown_mchbar(dev);

	destroy_workqueue(dev_priv->wq);

out_iomapfree:

out_mtrrfree:

	if (dev_priv->mm.gtt_mtrr >= 0) {

		mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,

			 dev->agp->agp_info.aper_size * 1024 * 1024);

		dev_priv->mm.gtt_mtrr = -1;

	}

	io_mapping_free(dev_priv->mm.gtt_mapping);

out_rmmap:

	pci_iounmap(dev->pdev, dev_priv->regs);