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Commit 57439e13 authored by Siddartha Mohanadoss's avatar Siddartha Mohanadoss Committed by Rama Krishna Phani A
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msm: ep_pcie: Initialize MHI MMIO once 



Initialize MHI MMIO during device initialization the
first time. For cases where the link shuts down without
device bootup the MMIO is not required to be reinitialized.
If the MMIO is reinitialized without device bootup it
causes the host and device to go out of sync.

Change-Id: I7188d3c6e9e79ff93c4b0ce0207cee5161ae519b
Signed-off-by: default avatarSiddartha Mohanadoss <smohanad@codeaurora.org>
parent 43a526a7

drivers/platform/msm/ep_pcie/ep_pcie_com.h

+1 −1
Original line number Original line Diff line number Diff line
@@ -359,7 +359,7 @@ struct ep_pcie_dev_t { 
	ulong                        global_irq_counter;

	ulong                        global_irq_counter;





	bool                         dump_conf;

	bool                         dump_conf;



	bool                         config_mmio_init;

	bool                         enumerated;

	bool                         enumerated;

	enum ep_pcie_link_status     link_status;

	enum ep_pcie_link_status     link_status;

	bool                         perst_deast;

	bool                         perst_deast;

drivers/platform/msm/ep_pcie/ep_pcie_core.c

+9 −0
Original line number Original line Diff line number Diff line
@@ -503,6 +503,13 @@ static void ep_pcie_config_mmio(struct ep_pcie_dev_t *dev) 
		"Initial version of MMIO is:0x%x\n",

		"Initial version of MMIO is:0x%x\n",

		readl_relaxed(dev->mmio + PCIE20_MHIVER));

		readl_relaxed(dev->mmio + PCIE20_MHIVER));





	if (dev->config_mmio_init) {

		EP_PCIE_DBG(dev,

			"PCIe V%d: MMIO already initialized, return\n",

				dev->rev);

		return;

	}



	ep_pcie_write_reg(dev->mmio, PCIE20_MHICFG, 0x02800880);

	ep_pcie_write_reg(dev->mmio, PCIE20_MHICFG, 0x02800880);

	ep_pcie_write_reg(dev->mmio, PCIE20_BHI_EXECENV, 0x2);

	ep_pcie_write_reg(dev->mmio, PCIE20_BHI_EXECENV, 0x2);

	ep_pcie_write_reg(dev->mmio, PCIE20_MHICTRL, 0x0);

	ep_pcie_write_reg(dev->mmio, PCIE20_MHICTRL, 0x0);
@@ -511,6 +518,8 @@ static void ep_pcie_config_mmio(struct ep_pcie_dev_t *dev) 
	ep_pcie_write_reg(dev->mmio, PCIE20_BHI_VERSION_LOWER, 0x2);

	ep_pcie_write_reg(dev->mmio, PCIE20_BHI_VERSION_LOWER, 0x2);

	ep_pcie_write_reg(dev->mmio, PCIE20_BHI_VERSION_UPPER, 0x1);

	ep_pcie_write_reg(dev->mmio, PCIE20_BHI_VERSION_UPPER, 0x1);

	ep_pcie_write_reg(dev->mmio, PCIE20_BHI_INTVEC, 0xffffffff);

	ep_pcie_write_reg(dev->mmio, PCIE20_BHI_INTVEC, 0xffffffff);



	dev->config_mmio_init = true;

}

}





static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured)

static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured)