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Commit 56e520c7 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'iommu-updates-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu 

Pull IOMMU updates from Joerg Roedel:

 - support for interrupt virtualization in the AMD IOMMU driver. These
   patches were shared with the KVM tree and are already merged through
   that tree.

 - generic DT-binding support for the ARM-SMMU driver. With this the
   driver now makes use of the generic DMA-API code. This also required
   some changes outside of the IOMMU code, but these are acked by the
   respective maintainers.

 - more cleanups and fixes all over the place.

* tag 'iommu-updates-v4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (40 commits)
  iommu/amd: No need to wait iommu completion if no dte irq entry change
  iommu/amd: Free domain id when free a domain of struct dma_ops_domain
  iommu/amd: Use standard bitmap operation to set bitmap
  iommu/amd: Clean up the cmpxchg64 invocation
  iommu/io-pgtable-arm: Check for v7s-incapable systems
  iommu/dma: Avoid PCI host bridge windows
  iommu/dma: Add support for mapping MSIs
  iommu/arm-smmu: Set domain geometry
  iommu/arm-smmu: Wire up generic configuration support
  Docs: dt: document ARM SMMU generic binding usage
  iommu/arm-smmu: Convert to iommu_fwspec
  iommu/arm-smmu: Intelligent SMR allocation
  iommu/arm-smmu: Add a stream map entry iterator
  iommu/arm-smmu: Streamline SMMU data lookups
  iommu/arm-smmu: Refactor mmu-masters handling
  iommu/arm-smmu: Keep track of S2CR state
  iommu/arm-smmu: Consolidate stream map entry state
  iommu/arm-smmu: Handle stream IDs more dynamically
  iommu/arm-smmu: Set PRIVCFG in stage 1 STEs
  iommu/arm-smmu: Support non-PCI devices with SMMUv3
  ...
parents d09ba131 13a08259

Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt

+7 −1
Original line number Diff line number Diff line
@@ -27,6 +27,12 @@ the PCIe specification. 
                      * "cmdq-sync" - CMD_SYNC complete

                      * "gerror"    - Global Error activated



- #iommu-cells      : See the generic IOMMU binding described in

                        devicetree/bindings/pci/pci-iommu.txt

                      for details. For SMMUv3, must be 1, with each cell

                      describing a single stream ID. All possible stream

                      IDs which a device may emit must be described.



** SMMUv3 optional properties:



- dma-coherent      : Present if DMA operations made by the SMMU (page
@@ -54,6 +60,6 @@ the PCIe specification. 
                             <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;

                interrupt-names = "eventq", "priq", "cmdq-sync", "gerror";

                dma-coherent;

                #iommu-cells = <0>;

                #iommu-cells = <1>;

                msi-parent = <&its 0xff0000>;

        };

Documentation/devicetree/bindings/iommu/arm,smmu.txt

+47 −14
Original line number Diff line number Diff line
@@ -35,12 +35,16 @@ conditions. 
                  interrupt per context bank. In the case of a single,

                  combined interrupt, it must be listed multiple times.



- mmu-masters   : A list of phandles to device nodes representing bus

                  masters for which the SMMU can provide a translation

                  and their corresponding StreamIDs (see example below).

                  Each device node linked from this list must have a

                  "#stream-id-cells" property, indicating the number of

                  StreamIDs associated with it.

- #iommu-cells  : See Documentation/devicetree/bindings/iommu/iommu.txt

                  for details. With a value of 1, each "iommus" entry

                  represents a distinct stream ID emitted by that device

                  into the relevant SMMU.



                  SMMUs with stream matching support and complex masters

                  may use a value of 2, where the second cell represents

                  an SMR mask to combine with the ID in the first cell.

                  Care must be taken to ensure the set of matched IDs

                  does not result in conflicts.



** System MMU optional properties:
@@ -56,9 +60,20 @@ conditions. 
                  aliases of secure registers have to be used during

                  SMMU configuration.



Example:

** Deprecated properties:



- mmu-masters (deprecated in favour of the generic "iommus" binding) :

                  A list of phandles to device nodes representing bus

                  masters for which the SMMU can provide a translation

                  and their corresponding Stream IDs. Each device node

                  linked from this list must have a "#stream-id-cells"

                  property, indicating the number of Stream ID

                  arguments associated with its phandle.



        smmu {

** Examples:



        /* SMMU with stream matching or stream indexing */

        smmu1: iommu {

                compatible = "arm,smmu-v1";

                reg = <0xba5e0000 0x10000>;

                #global-interrupts = <2>;
@@ -68,11 +83,29 @@ Example: 
                             <0 35 4>,

                             <0 36 4>,

                             <0 37 4>;

                #iommu-cells = <1>;

        };



        /* device with two stream IDs, 0 and 7 */

        master1 {

                iommus = <&smmu1 0>,

                         <&smmu1 7>;

        };





        /* SMMU with stream matching */

        smmu2: iommu {

                ...

                #iommu-cells = <2>;

        };



        /* device with stream IDs 0 and 7 */

        master2 {

                iommus = <&smmu2 0 0>,

                         <&smmu2 7 0>;

        };



                /*

                 * Two DMA controllers, the first with two StreamIDs (0xd01d

                 * and 0xd01e) and the second with only one (0xd11c).

                 */

                mmu-masters = <&dma0 0xd01d 0xd01e>,

                              <&dma1 0xd11c>;

        /* device with stream IDs 1, 17, 33 and 49 */

        master3 {

                iommus = <&smmu2 1 0x30>;

        };

Documentation/devicetree/bindings/pci/pci-iommu.txt

0 → 100644
+171 −0
Original line number Diff line number Diff line 
This document describes the generic device tree binding for describing the

relationship between PCI(e) devices and IOMMU(s).



Each PCI(e) device under a root complex is uniquely identified by its Requester

ID (AKA RID). A Requester ID is a triplet of a Bus number, Device number, and

Function number.



For the purpose of this document, when treated as a numeric value, a RID is

formatted such that:



* Bits [15:8] are the Bus number.

* Bits [7:3] are the Device number.

* Bits [2:0] are the Function number.

* Any other bits required for padding must be zero.



IOMMUs may distinguish PCI devices through sideband data derived from the

Requester ID. While a given PCI device can only master through one IOMMU, a

root complex may split masters across a set of IOMMUs (e.g. with one IOMMU per

bus).



The generic 'iommus' property is insufficient to describe this relationship,

and a mechanism is required to map from a PCI device to its IOMMU and sideband

data.



For generic IOMMU bindings, see

Documentation/devicetree/bindings/iommu/iommu.txt.





PCI root complex

================



Optional properties

-------------------



- iommu-map: Maps a Requester ID to an IOMMU and associated iommu-specifier

  data.



  The property is an arbitrary number of tuples of

  (rid-base,iommu,iommu-base,length).



  Any RID r in the interval [rid-base, rid-base + length) is associated with

  the listed IOMMU, with the iommu-specifier (r - rid-base + iommu-base).



- iommu-map-mask: A mask to be applied to each Requester ID prior to being

  mapped to an iommu-specifier per the iommu-map property.





Example (1)

===========



/ {

	#address-cells = <1>;

	#size-cells = <1>;



	iommu: iommu@a {

		reg = <0xa 0x1>;

		compatible = "vendor,some-iommu";

		#iommu-cells = <1>;

	};



	pci: pci@f {

		reg = <0xf 0x1>;

		compatible = "vendor,pcie-root-complex";

		device_type = "pci";



		/*

		 * The sideband data provided to the IOMMU is the RID,

		 * identity-mapped.

		 */

		iommu-map = <0x0 &iommu 0x0 0x10000>;

	};

};





Example (2)

===========



/ {

	#address-cells = <1>;

	#size-cells = <1>;



	iommu: iommu@a {

		reg = <0xa 0x1>;

		compatible = "vendor,some-iommu";

		#iommu-cells = <1>;

	};



	pci: pci@f {

		reg = <0xf 0x1>;

		compatible = "vendor,pcie-root-complex";

		device_type = "pci";



		/*

		 * The sideband data provided to the IOMMU is the RID with the

		 * function bits masked out.

		 */

		iommu-map = <0x0 &iommu 0x0 0x10000>;

		iommu-map-mask = <0xfff8>;

	};

};





Example (3)

===========



/ {

	#address-cells = <1>;

	#size-cells = <1>;



	iommu: iommu@a {

		reg = <0xa 0x1>;

		compatible = "vendor,some-iommu";

		#iommu-cells = <1>;

	};



	pci: pci@f {

		reg = <0xf 0x1>;

		compatible = "vendor,pcie-root-complex";

		device_type = "pci";



		/*

		 * The sideband data provided to the IOMMU is the RID,

		 * but the high bits of the bus number are flipped.

		 */

		iommu-map = <0x0000 &iommu 0x8000 0x8000>,

			    <0x8000 &iommu 0x0000 0x8000>;

	};

};





Example (4)

===========



/ {

	#address-cells = <1>;

	#size-cells = <1>;



	iommu_a: iommu@a {

		reg = <0xa 0x1>;

		compatible = "vendor,some-iommu";

		#iommu-cells = <1>;

	};



	iommu_b: iommu@b {

		reg = <0xb 0x1>;

		compatible = "vendor,some-iommu";

		#iommu-cells = <1>;

	};



	iommu_c: iommu@c {

		reg = <0xc 0x1>;

		compatible = "vendor,some-iommu";

		#iommu-cells = <1>;

	};



	pci: pci@f {

		reg = <0xf 0x1>;

		compatible = "vendor,pcie-root-complex";

		device_type = "pci";



		/*

		 * Devices with bus number 0-127 are mastered via IOMMU

		 * a, with sideband data being RID[14:0].

		 * Devices with bus number 128-255 are mastered via

		 * IOMMU b, with sideband data being RID[14:0].

		 * No devices master via IOMMU c.

		 */

		iommu-map = <0x0000 &iommu_a 0x0000 0x8000>,

			    <0x8000 &iommu_b 0x0000 0x8000>;

	};

};

arch/arm64/mm/dma-mapping.c

+1 −1
Original line number Diff line number Diff line
@@ -828,7 +828,7 @@ static bool do_iommu_attach(struct device *dev, const struct iommu_ops *ops, 
	 * then the IOMMU core will have already configured a group for this

	 * device, and allocated the default domain for that group.

	 */

	if (!domain || iommu_dma_init_domain(domain, dma_base, size)) {

	if (!domain || iommu_dma_init_domain(domain, dma_base, size, dev)) {

		pr_warn("Failed to set up IOMMU for device %s; retaining platform DMA ops\n",

			dev_name(dev));

		return false;

arch/x86/configs/x86_64_defconfig

+0 −1
Original line number Diff line number Diff line
@@ -255,7 +255,6 @@ CONFIG_RTC_CLASS=y 
CONFIG_DMADEVICES=y

CONFIG_EEEPC_LAPTOP=y

CONFIG_AMD_IOMMU=y

CONFIG_AMD_IOMMU_STATS=y

CONFIG_INTEL_IOMMU=y

# CONFIG_INTEL_IOMMU_DEFAULT_ON is not set

CONFIG_EFI_VARS=y