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Commit 56aebae0 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman
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arm64: dts: r8a7796: Add SYSC PM Domains 



Add a device node for the System Controller.
Hook up the Cortex-A57 CPU core and L2 cache/SCU to their respective PM
Domains.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 006e1db8

arch/arm64/boot/dts/renesas/r8a7796.dtsi

+9 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 


#include <dt-bindings/clock/r8a7796-cpg-mssr.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/power/r8a7796-sysc.h>



/ {

	compatible = "renesas,r8a7796";
@@ -30,6 +31,7 @@ 
			compatible = "arm,cortex-a57", "arm,armv8";

			reg = <0x0>;

			device_type = "cpu";

			power-domains = <&sysc R8A7796_PD_CA57_CPU0>;

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

		};
@@ -37,6 +39,7 @@ 
		L2_CA57: cache-controller@0 {

			compatible = "cache";

			reg = <0>;

			power-domains = <&sysc R8A7796_PD_CA57_SCU>;

			cache-unified;

			cache-level = <2>;

		};
@@ -104,6 +107,12 @@ 
			#power-domain-cells = <0>;

		};



		sysc: system-controller@e6180000 {

			compatible = "renesas,r8a7796-sysc";

			reg = <0 0xe6180000 0 0x0400>;

			#power-domain-cells = <1>;

		};



		scif2: serial@e6e88000 {

			compatible = "renesas,scif-r8a7796",

				     "renesas,rcar-gen3-scif", "renesas,scif";