Merge branch 'clk-renesas-for-v4.7' of... (56ad09e2) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/clk/renesas/clk-mstp.c

+2 −5

Original line number	Original line	Diff line number	Diff line
	@@ -243,9 +243,7 @@ static void __init cpg_mstp_clocks_init(struct device_node *np)
	}		}
	CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);		CLK_OF_DECLARE(cpg_mstp_clks, "renesas,cpg-mstp-clocks", cpg_mstp_clocks_init);

			int cpg_mstp_attach_dev(struct generic_pm_domain unused, struct device dev)
	#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
	int cpg_mstp_attach_dev(struct generic_pm_domain domain, struct device dev)
	{		{
	struct device_node *np = dev->of_node;		struct device_node *np = dev->of_node;
	struct of_phandle_args clkspec;		struct of_phandle_args clkspec;
	@@ -297,7 +295,7 @@ int cpg_mstp_attach_dev(struct generic_pm_domain domain, struct device dev)
	return error;		return error;
	}		}

	void cpg_mstp_detach_dev(struct generic_pm_domain domain, struct device dev)		void cpg_mstp_detach_dev(struct generic_pm_domain unused, struct device dev)
	{		{
	if (!list_empty(&dev->power.subsys_data->clock_list))		if (!list_empty(&dev->power.subsys_data->clock_list))
	pm_clk_destroy(dev);		pm_clk_destroy(dev);
	@@ -326,4 +324,3 @@ void __init cpg_mstp_add_clk_domain(struct device_node *np)

	of_genpd_add_provider_simple(np, pd);		of_genpd_add_provider_simple(np, pd);
	}		}
	#endif /* !CONFIG_PM_GENERIC_DOMAINS_OF */

drivers/clk/renesas/r8a7795-cpg-mssr.c

+30 −4

Original line number	Original line	Diff line number	Diff line
	@@ -13,6 +13,7 @@
	*/		*/

	#include <linux/bug.h>		#include <linux/bug.h>
			#include <linux/clk.h>
	#include <linux/clk-provider.h>		#include <linux/clk-provider.h>
	#include <linux/device.h>		#include <linux/device.h>
	#include <linux/err.h>		#include <linux/err.h>
	@@ -26,6 +27,7 @@

	#include "renesas-cpg-mssr.h"		#include "renesas-cpg-mssr.h"

			#define CPG_RCKCR 0x240

	enum clk_ids {		enum clk_ids {
	/* Core Clock Outputs exported to DT */		/* Core Clock Outputs exported to DT */
	@@ -50,6 +52,7 @@ enum clk_ids {
	CLK_S3,		CLK_S3,
	CLK_SDSRC,		CLK_SDSRC,
	CLK_SSPSRC,		CLK_SSPSRC,
			CLK_RINT,

	/* Module Clocks */		/* Module Clocks */
	MOD_CLK_BASE		MOD_CLK_BASE
	@@ -63,8 +66,12 @@ enum r8a7795_clk_types {
	CLK_TYPE_GEN3_PLL3,		CLK_TYPE_GEN3_PLL3,
	CLK_TYPE_GEN3_PLL4,		CLK_TYPE_GEN3_PLL4,
	CLK_TYPE_GEN3_SD,		CLK_TYPE_GEN3_SD,
			CLK_TYPE_GEN3_R,
	};		};

			#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
			DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)

	static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {		static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
	/* External Clock Inputs */		/* External Clock Inputs */
	DEF_INPUT("extal", CLK_EXTAL),		DEF_INPUT("extal", CLK_EXTAL),
	@@ -102,10 +109,10 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
	DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),		DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
	DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),		DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),

	DEF_SD("sd0", R8A7795_CLK_SD0, CLK_PLL1_DIV2, 0x0074),		DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_PLL1_DIV2, 0x0074),
	DEF_SD("sd1", R8A7795_CLK_SD1, CLK_PLL1_DIV2, 0x0078),		DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_PLL1_DIV2, 0x0078),
	DEF_SD("sd2", R8A7795_CLK_SD2, CLK_PLL1_DIV2, 0x0268),		DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_PLL1_DIV2, 0x0268),
	DEF_SD("sd3", R8A7795_CLK_SD3, CLK_PLL1_DIV2, 0x026c),		DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_PLL1_DIV2, 0x026c),

	DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),		DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
	DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),		DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
	@@ -113,6 +120,11 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
	DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),		DEF_DIV6P1("mso", R8A7795_CLK_MSO, CLK_PLL1_DIV4, 0x014),
	DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250),		DEF_DIV6P1("hdmi", R8A7795_CLK_HDMI, CLK_PLL1_DIV2, 0x250),
	DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),		DEF_DIV6P1("canfd", R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),

			DEF_DIV6_RO("osc", R8A7795_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
			DEF_DIV6_RO("r_int", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),

			DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
	};		};

	static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {		static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
	@@ -139,6 +151,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
	DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),		DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
	DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),		DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
	DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),		DEF_MOD("usb-dmac1", 331, R8A7795_CLK_S3D1),
			DEF_MOD("rwdt0", 402, R8A7795_CLK_R),
	DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),		DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
	DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),		DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1),
	DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4),		DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4),
	@@ -148,6 +161,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {
	DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),		DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
	DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),		DEF_MOD("hscif1", 519, R8A7795_CLK_S3D1),
	DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),		DEF_MOD("hscif0", 520, R8A7795_CLK_S3D1),
			DEF_MOD("pwm", 523, R8A7795_CLK_S3D4),
	DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1),		DEF_MOD("fcpvd3", 600, R8A7795_CLK_S2D1),
	DEF_MOD("fcpvd2", 601, R8A7795_CLK_S2D1),		DEF_MOD("fcpvd2", 601, R8A7795_CLK_S2D1),
	DEF_MOD("fcpvd1", 602, R8A7795_CLK_S2D1),		DEF_MOD("fcpvd1", 602, R8A7795_CLK_S2D1),
	@@ -578,6 +592,18 @@ struct clk * __init r8a7795_cpg_clk_register(struct device *dev,
	case CLK_TYPE_GEN3_SD:		case CLK_TYPE_GEN3_SD:
	return cpg_sd_clk_register(core, base, __clk_get_name(parent));		return cpg_sd_clk_register(core, base, __clk_get_name(parent));

			case CLK_TYPE_GEN3_R:
			/* RINT is default. Only if EXTALR is populated, we switch to it */
			value = readl(base + CPG_RCKCR) & 0x3f;

			if (clk_get_rate(clks[CLK_EXTALR])) {
			parent = clks[CLK_EXTALR];
			value \|= BIT(15);
			}

			writel(value, base + CPG_RCKCR);
			break;

	default:		default:
	return ERR_PTR(-EINVAL);		return ERR_PTR(-EINVAL);
	}		}

drivers/clk/renesas/renesas-cpg-mssr.c

+12 −17

Original line number	Original line	Diff line number	Diff line
	@@ -253,7 +253,7 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
	{		{
	struct clk clk = NULL, parent;		struct clk clk = NULL, parent;
	struct device *dev = priv->dev;		struct device *dev = priv->dev;
	unsigned int id = core->id;		unsigned int id = core->id, div = core->div;
	const char *parent_name;		const char *parent_name;

	WARN_DEBUG(id >= priv->num_core_clks);		WARN_DEBUG(id >= priv->num_core_clks);
	@@ -266,6 +266,7 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,

	case CLK_TYPE_FF:		case CLK_TYPE_FF:
	case CLK_TYPE_DIV6P1:		case CLK_TYPE_DIV6P1:
			case CLK_TYPE_DIV6_RO:
	WARN_DEBUG(core->parent >= priv->num_core_clks);		WARN_DEBUG(core->parent >= priv->num_core_clks);
	parent = priv->clks[core->parent];		parent = priv->clks[core->parent];
	if (IS_ERR(parent)) {		if (IS_ERR(parent)) {
	@@ -274,13 +275,18 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
	}		}

	parent_name = __clk_get_name(parent);		parent_name = __clk_get_name(parent);
	if (core->type == CLK_TYPE_FF) {
	clk = clk_register_fixed_factor(NULL, core->name,		if (core->type == CLK_TYPE_DIV6_RO)
	parent_name, 0,		/* Multiply with the DIV6 register value */
	core->mult, core->div);		div *= (readl(priv->base + core->offset) & 0x3f) + 1;
	} else {
			if (core->type == CLK_TYPE_DIV6P1) {
	clk = cpg_div6_register(core->name, 1, &parent_name,		clk = cpg_div6_register(core->name, 1, &parent_name,
	priv->base + core->offset);		priv->base + core->offset);
			} else {
			clk = clk_register_fixed_factor(NULL, core->name,
			parent_name, 0,
			core->mult, div);
	}		}
	break;		break;

	@@ -375,8 +381,6 @@ static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod,
	kfree(clock);		kfree(clock);
	}		}


	#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
	struct cpg_mssr_clk_domain {		struct cpg_mssr_clk_domain {
	struct generic_pm_domain genpd;		struct generic_pm_domain genpd;
	struct device_node *np;		struct device_node *np;
	@@ -491,15 +495,6 @@ static int __init cpg_mssr_add_clk_domain(struct device *dev,
	of_genpd_add_provider_simple(np, genpd);		of_genpd_add_provider_simple(np, genpd);
	return 0;		return 0;
	}		}
	#else
	static inline int cpg_mssr_add_clk_domain(struct device *dev,
	const unsigned int *core_pm_clks,
	unsigned int num_core_pm_clks)
	{
	return 0;
	}
	#endif /* !CONFIG_PM_GENERIC_DOMAINS_OF */


	static const struct of_device_id cpg_mssr_match[] = {		static const struct of_device_id cpg_mssr_match[] = {
	#ifdef CONFIG_ARCH_R8A7795		#ifdef CONFIG_ARCH_R8A7795

drivers/clk/renesas/renesas-cpg-mssr.h

+3 −3

Original line number	Original line	Diff line number	Diff line
	@@ -37,6 +37,7 @@ enum clk_types {
	CLK_TYPE_IN, /* External Clock Input */		CLK_TYPE_IN, /* External Clock Input */
	CLK_TYPE_FF, /* Fixed Factor Clock */		CLK_TYPE_FF, /* Fixed Factor Clock */
	CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */		CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
			CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */

	/* Custom definitions start here */		/* Custom definitions start here */
	CLK_TYPE_CUSTOM,		CLK_TYPE_CUSTOM,
	@@ -53,9 +54,8 @@ enum clk_types {
	DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)		DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
	#define DEF_DIV6P1(_name, _id, _parent, _offset) \		#define DEF_DIV6P1(_name, _id, _parent, _offset) \
	DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)		DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
	#define DEF_SD(_name, _id, _parent, _offset) \		#define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
	DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)		DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)


	/*		/*
	* Definitions of Module Clocks		* Definitions of Module Clocks

include/linux/clk/renesas.h

+2 −6

Original line number	Original line	Diff line number	Diff line
	@@ -24,12 +24,8 @@ void r8a7778_clocks_init(u32 mode);
	void r8a7779_clocks_init(u32 mode);		void r8a7779_clocks_init(u32 mode);
	void rcar_gen2_clocks_init(u32 mode);		void rcar_gen2_clocks_init(u32 mode);

	#ifdef CONFIG_PM_GENERIC_DOMAINS_OF
	void cpg_mstp_add_clk_domain(struct device_node *np);		void cpg_mstp_add_clk_domain(struct device_node *np);
	int cpg_mstp_attach_dev(struct generic_pm_domain domain, struct device dev);		int cpg_mstp_attach_dev(struct generic_pm_domain unused, struct device dev);
	void cpg_mstp_detach_dev(struct generic_pm_domain domain, struct device dev);		void cpg_mstp_detach_dev(struct generic_pm_domain unused, struct device dev);
	#else
	static inline void cpg_mstp_add_clk_domain(struct device_node *np) {}
	#endif

	#endif		#endif