Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 56a0eccd authored by Chanho Min's avatar Chanho Min Committed by Olof Johansson
Browse files

arm64: dts: Add dts files for LG Electronics's lg1312 SoC 



Add initial dtsi file to support lg1312 SoC which based on
Cortex-A53. Also add dts file to support lg1312 reference board
which based on lg1312 SoC.

Signed-off-by: default avatarChanho Min <chanho.min@lge.com>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent 49695dfa

arch/arm64/boot/dts/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ dts-dirs += rockchip 
dts-dirs += socionext

dts-dirs += sprd

dts-dirs += xilinx

dts-dirs += lg



subdir-y	:= $(dts-dirs)

arch/arm64/boot/dts/lg/Makefile

0 → 100644
+5 −0
Original line number Diff line number Diff line 
dtb-$(CONFIG_ARCH_LG1K) += lg1312-ref.dtb



always		:= $(dtb-y)

subdir-y	:= $(dts-dirs)

clean-files	:= *.dtb

arch/arm64/boot/dts/lg/lg1312-ref.dts

0 → 100644
+36 −0
Original line number Diff line number Diff line 
/*

 * dts file for lg1312 Reference Board.

 *

 * Copyright (C) 2016, LG Electronics

 */



/dts-v1/;



#include "lg1312.dtsi"



/ {

	#address-cells = <2>;

	#size-cells = <1>;



	model = "LG Electronics, DTV SoC LG1312 Reference Board";

	compatible = "lge,lg1312-ref", "lge,lg1312";



	aliases {

		serial0 = &uart0;

		serial1 = &uart1;

		serial2 = &uart2;

	};



	memory {

		device_type = "memory";

		reg = <0x0 0x00000000 0x20000000>;

	};



	chosen {

		stdout-path = "serial0:115200n8";

	};

};



&uart0 {

	status = "okay";

};

arch/arm64/boot/dts/lg/lg1312.dtsi

0 → 100644
+351 −0
Original line number Diff line number Diff line 
/*

 * dts file for lg1312 SoC

 *

 * Copyright (C) 2016, LG Electronics

 */



#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	#address-cells = <2>;

	#size-cells = <2>;



	compatible = "lge,lg1312";

	interrupt-parent = <&gic>;



	cpus {

		#address-cells = <2>;

		#size-cells = <0>;



		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x0>;

			next-level-cache = <&L2_0>;

		};

		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x1>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

		};

		cpu2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x2>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

		};

		cpu3: cpu@3 {

			device_type = "cpu";

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x0 0x3>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

		};

		L2_0: l2-cache0 {

			compatible = "cache";

		};

	};



	psci {

		compatible  = "arm,psci-0.2", "arm,psci";

		method = "smc";

		cpu_suspend = <0x84000001>;

		cpu_off = <0x84000002>;

		cpu_on = <0x84000003>;

	};



	gic: interrupt-controller@c0001000 {

		#interrupt-cells = <3>;

		compatible = "arm,gic-400";

		interrupt-controller;

		reg = <0x0 0xc0001000 0x1000>,

		      <0x0 0xc0002000 0x2000>,

		      <0x0 0xc0004000 0x2000>,

		      <0x0 0xc0006000 0x2000>;

	};



	pmu {

		compatible = "arm,cortex-a53-pmu";

		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-affinity = <&cpu0>,

				     <&cpu1>,

				     <&cpu2>,

				     <&cpu3>;

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) |

			      IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) |

			      IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) |

			      IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) |

			      IRQ_TYPE_LEVEL_LOW)>;

	};



	clk_bus: clk_bus {

		#clock-cells = <0>;



		compatible = "fixed-clock";

		clock-frequency = <198000000>;

		clock-output-names = "BUSCLK";

	};



	soc {

		#address-cells = <2>;

		#size-cells = <1>;



		compatible = "simple-bus";

		interrupt-parent = <&gic>;

		ranges;



		eth0: ethernet@c1b00000 {

			compatible = "cdns,gem";

			reg = <0x0 0xc1b00000 0x1000>;

			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_bus>, <&clk_bus>;

			clock-names = "hclk", "pclk";

			phy-mode = "rmii";

			/* Filled in by boot */

			mac-address = [ 00 00 00 00 00 00 ];

		};

	};



	amba {

		#address-cells = <2>;

		#size-cells = <1>;

		#interrupts-cells = <3>;



		compatible = "arm,amba-bus";

		interrupt-parent = <&gic>;

		ranges;



		timers: timer@fd100000 {

			compatible = "arm,sp804";

			reg = <0x0 0xfd100000 0x1000>;

			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

		};

		wdog: watchdog@fd200000 {

			compatible = "arm,sp805", "arm,primecell";

			reg = <0x0 0xfd200000 0x1000>;

			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

		};

		uart0: serial@fe000000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0x0 0xfe000000 0x1000>;

			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

			status="disabled";

		};

		uart1: serial@fe100000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0x0 0xfe100000 0x1000>;

			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

			status="disabled";

		};

		uart2: serial@fe200000 {

			compatible = "arm,pl011", "arm,primecell";

			reg = <0x0 0xfe200000 0x1000>;

			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

			status="disabled";

		};

		spi0: ssp@fe800000 {

			compatible = "arm,pl022", "arm,primecell";

			reg = <0x0 0xfe800000 0x1000>;

			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

		};

		spi1: ssp@fe900000 {

			compatible = "arm,pl022", "arm,primecell";

			reg = <0x0 0xfe900000 0x1000>;

			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

		};

		dmac0: dma@c1128000 {

			compatible = "arm,pl330", "arm,primecell";

			reg = <0x0 0xc1128000 0x1000>;

			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

		};

		gpio0: gpio@fd400000 {

			#gpio-cells = <2>;

			compatible = "arm,pl061", "arm,primecell";

			gpio-controller;

			reg = <0x0 0xfd400000 0x1000>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

			status="disabled";

		};

		gpio1: gpio@fd410000 {

			#gpio-cells = <2>;

			compatible = "arm,pl061", "arm,primecell";

			gpio-controller;

			reg = <0x0 0xfd410000 0x1000>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

			status="disabled";

		};

		gpio2: gpio@fd420000 {

			#gpio-cells = <2>;

			compatible = "arm,pl061", "arm,primecell";

			gpio-controller;

			reg = <0x0 0xfd420000 0x1000>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

			status="disabled";

		};

		gpio3: gpio@fd430000 {

			#gpio-cells = <2>;

			compatible = "arm,pl061", "arm,primecell";

			gpio-controller;

			reg = <0x0 0xfd430000 0x1000>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

		};

		gpio4: gpio@fd440000 {

			#gpio-cells = <2>;

			compatible = "arm,pl061", "arm,primecell";

			gpio-controller;

			reg = <0x0 0xfd440000 0x1000>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

			status="disabled";

		};

		gpio5: gpio@fd450000 {

			#gpio-cells = <2>;

			compatible = "arm,pl061", "arm,primecell";

			gpio-controller;

			reg = <0x0 0xfd450000 0x1000>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

			status="disabled";

		};

		gpio6: gpio@fd460000 {

			#gpio-cells = <2>;

			compatible = "arm,pl061", "arm,primecell";

			gpio-controller;

			reg = <0x0 0xfd460000 0x1000>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

			status="disabled";

		};

		gpio7: gpio@fd470000 {

			#gpio-cells = <2>;

			compatible = "arm,pl061", "arm,primecell";

			gpio-controller;

			reg = <0x0 0xfd470000 0x1000>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

			status="disabled";

		};

		gpio8: gpio@fd480000 {

			#gpio-cells = <2>;

			compatible = "arm,pl061", "arm,primecell";

			gpio-controller;

			reg = <0x0 0xfd480000 0x1000>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

			status="disabled";

		};

		gpio9: gpio@fd490000 {

			#gpio-cells = <2>;

			compatible = "arm,pl061", "arm,primecell";

			gpio-controller;

			reg = <0x0 0xfd490000 0x1000>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

			status="disabled";

		};

		gpio10: gpio@fd4a0000 {

			#gpio-cells = <2>;

			compatible = "arm,pl061", "arm,primecell";

			gpio-controller;

			reg = <0x0 0xfd4a0000 0x1000>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

			status="disabled";

		};

		gpio11: gpio@fd4b0000 {

			#gpio-cells = <2>;

			compatible = "arm,pl061", "arm,primecell";

			gpio-controller;

			reg = <0x0 0xfd4b0000 0x1000>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

		};

		gpio12: gpio@fd4c0000 {

			#gpio-cells = <2>;

			compatible = "arm,pl061", "arm,primecell";

			gpio-controller;

			reg = <0x0 0xfd4c0000 0x1000>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

			status="disabled";

		};

		gpio13: gpio@fd4d0000 {

			#gpio-cells = <2>;

			compatible = "arm,pl061", "arm,primecell";

			gpio-controller;

			reg = <0x0 0xfd4d0000 0x1000>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

			status="disabled";

		};

		gpio14: gpio@fd4e0000 {

			#gpio-cells = <2>;

			compatible = "arm,pl061", "arm,primecell";

			gpio-controller;

			reg = <0x0 0xfd4e0000 0x1000>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

			status="disabled";

		};

		gpio15: gpio@fd4f0000 {

			#gpio-cells = <2>;

			compatible = "arm,pl061", "arm,primecell";

			gpio-controller;

			reg = <0x0 0xfd4f0000 0x1000>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

			status="disabled";

		};

		gpio16: gpio@fd500000 {

			#gpio-cells = <2>;

			compatible = "arm,pl061", "arm,primecell";

			gpio-controller;

			reg = <0x0 0xfd500000 0x1000>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

			status="disabled";

		};

		gpio17: gpio@fd510000 {

			#gpio-cells = <2>;

			compatible = "arm,pl061", "arm,primecell";

			gpio-controller;

			reg = <0x0 0xfd510000 0x1000>;

			clocks = <&clk_bus>;

			clock-names = "apb_pclk";

		};

	};

};