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Commit 56107780 authored by Harshdeep Dhatt's avatar Harshdeep Dhatt
Browse files

msm: kgsl: Take gpu snapshot if fenced write fails 



When write to a fenced register fails, take a gpu snapshot.

Change-Id: I9c0dd060b7064930866f43e4dcdf4a20393fb662
Signed-off-by: default avatarHarshdeep Dhatt <hdhatt@codeaurora.org>
parent af4ea937

drivers/gpu/msm/adreno.h

+1 −1
Original line number Diff line number Diff line
@@ -1955,7 +1955,7 @@ static inline int adreno_vbif_clear_pending_transactions( 
	return ret;

}



void adreno_gmu_fenced_write(struct adreno_device *adreno_dev,

int adreno_gmu_fenced_write(struct adreno_device *adreno_dev,

	enum adreno_regs offset, unsigned int val,

	unsigned int fence_mask);

#endif /*__ADRENO_H */

drivers/gpu/msm/adreno_ringbuffer.c

+6 −1
Original line number Diff line number Diff line
@@ -89,6 +89,7 @@ static void adreno_ringbuffer_wptr(struct adreno_device *adreno_dev, 
		struct adreno_ringbuffer *rb)

{

	unsigned long flags;

	int ret = 0;



	spin_lock_irqsave(&rb->preempt_lock, flags);

	if (adreno_in_preempt_state(adreno_dev, ADRENO_PREEMPT_NONE)) {
@@ -104,7 +105,7 @@ static void adreno_ringbuffer_wptr(struct adreno_device *adreno_dev, 
			 * Ensure the write posted after a possible

			 * GMU wakeup (write could have dropped during wakeup)

			 */

			adreno_gmu_fenced_write(adreno_dev,

			ret = adreno_gmu_fenced_write(adreno_dev,

				ADRENO_REG_CP_RB_WPTR, rb->_wptr,

				FENCE_STATUS_WRITEDROPPED0_MASK);
@@ -113,6 +114,10 @@ static void adreno_ringbuffer_wptr(struct adreno_device *adreno_dev, 


	rb->wptr = rb->_wptr;

	spin_unlock_irqrestore(&rb->preempt_lock, flags);



	if (ret)

		kgsl_device_snapshot(KGSL_DEVICE(adreno_dev), NULL, false);



}



void adreno_ringbuffer_submit(struct adreno_ringbuffer *rb,

drivers/gpu/msm/kgsl_gmu.c

+4 −3
Original line number Diff line number Diff line
@@ -1630,7 +1630,7 @@ void gmu_remove(struct kgsl_device *device) 
 * the write to the fenced register went through. If it didn't then we retry

 * the write until it goes through or we time out.

 */

void adreno_gmu_fenced_write(struct adreno_device *adreno_dev,

int adreno_gmu_fenced_write(struct adreno_device *adreno_dev,

		enum adreno_regs offset, unsigned int val,

		unsigned int fence_mask)

{
@@ -1639,7 +1639,7 @@ void adreno_gmu_fenced_write(struct adreno_device *adreno_dev, 
	adreno_writereg(adreno_dev, offset, val);



	if (!kgsl_gmu_isenabled(KGSL_DEVICE(adreno_dev)))

		return;

		return 0;



	for (i = 0; i < GMU_WAKEUP_RETRY_MAX; i++) {

		adreno_read_gmureg(adreno_dev, ADRENO_REG_GMU_AHB_FENCE_STATUS,
@@ -1650,7 +1650,7 @@ void adreno_gmu_fenced_write(struct adreno_device *adreno_dev, 
		 * was successful

		 */

		if (!(status & fence_mask))

			return;

			return 0;

		/* Wait a small amount of time before trying again */

		udelay(GMU_WAKEUP_DELAY_US);
@@ -1660,4 +1660,5 @@ void adreno_gmu_fenced_write(struct adreno_device *adreno_dev, 


	dev_err(adreno_dev->dev.dev,

		"GMU fenced register write timed out: reg %x\n", offset);

	return -ETIMEDOUT;

}