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Commit 55967afa authored by Suzuki K. Poulose's avatar Suzuki K. Poulose Committed by Kyle Yan
Browse files

arm64: Add work around for Arm Cortex-A55 Erratum 1024718 



Some variants of the Arm Cortex-55 cores (r0p0, r0p1, r1p0) suffer
from an erratum 1024718, which causes incorrect updates when DBM/AP
bits in a page table entry is modified without a break-before-make
sequence. The work around is to disable the hardware DBM feature
on the affected cores. The hardware Access Flag management features
is not affected.

The hardware DBM feature is a non-conflicting capability, i.e, the
kernel could handle cores using the feature and those without having
the features running at the same time. So this work around is detected
at early boot time, rather than delaying it until the CPUs are brought
up into the kernel with MMU turned on. This also avoids other complexities
with late CPUs turning online, with or without the hardware DBM features.

Change-Id: Idcd77182befaba2b459ccf4f7424c8c4557089d5
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Patch-mainline: linux-arm-kernel @ 01/16/2018, 10:23
[kyan@codeaurora.org: resolve trivial merge conflicts]
Signed-off-by: default avatarKyle Yan <kyan@codeaurora.org>
parent 4dcafb42

Documentation/arm64/silicon-errata.txt

+1 −0
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ stable kernels. 
| ARM            | Cortex-A57      | #852523         | N/A                         |

| ARM            | Cortex-A57      | #834220         | ARM64_ERRATUM_834220        |

| ARM            | Cortex-A72      | #853709         | N/A                         |

| ARM            | Cortex-A55      | #1024718        | ARM64_ERRATUM_1024718       |

| ARM            | MMU-500         | #841119,#826419 | N/A                         |

|                |                 |                 |                             |

| Cavium         | ThunderX ITS    | #22375, #24313  | CAVIUM_ERRATUM_22375        |

arch/arm64/Kconfig

+14 −0
Original line number Diff line number Diff line
@@ -432,6 +432,20 @@ config ARM64_ERRATUM_843419 


	  If unsure, say Y.



config ARM64_ERRATUM_1024718

	bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"

	default y

	help

	  This option adds work around for Arm Cortex-A55 Erratum 1024718.



	  Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect

	  update of the hardware dirty bit when the DBM/AP bits are updated

	  without a break-before-make. The work around is to disable the usage

	  of hardware DBM locally on the affected cores. CPUs not affected by

	  erratum will continue to use the feature.



	  If unsure, say Y.



config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

arch/arm64/mm/proc.S

+6 −0
Original line number Diff line number Diff line
@@ -290,6 +290,12 @@ ENTRY(__cpu_setup) 
	cbz	x9, 2f

	cmp	x9, #2

	b.lt	1f

#ifdef CONFIG_ARM64_ERRATUM_1024718

	/* Disable hardware DBM on Cortex-A55 r0p0, r0p1 & r1p0 */

	cpu_midr_match MIDR_CORTEX_A55, MIDR_CPU_VAR_REV(0, 0),\

			MIDR_CPU_VAR_REV(1, 0), x1, x2, x3, x4

	cbnz	x1, 1f

#endif

	orr	x10, x10, #TCR_HD		// hardware Dirty flag update

1:	orr	x10, x10, #TCR_HA		// hardware Access flag update

2: