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Commit 55963c9f authored by Sudeep Holla's avatar Sudeep Holla Committed by Thomas Gleixner
Browse files

irqchip: gic: Simplify gic_configure_irq by using IRQCHIP_SET_TYPE_MASKED 



GIC requires to disable the interrupt before changing the trigger type.
irqchip core provides IRQCHIP_SET_TYPE_MASKED flag and ensures that the
interrupt is masked before calling chip.irq_set_type() if the irqchip
sets the flag.

This patch adds IRQCHIP_SET_TYPE_MASKED to GIC irqchip so that the core
can manage disabling the interrupt while changing the trigger type.

Signed-off-by: default avatarSudeep Holla <sudeep.holla@arm.com>
Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Link: http://lkml.kernel.org/r/1433501997-19205-1-git-send-email-sudeep.holla@arm.com


Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 496c28b1

drivers/irqchip/irq-gic-common.c

+0 −17
Original line number Original line Diff line number Diff line
@@ -24,11 +24,8 @@ 
int gic_configure_irq(unsigned int irq, unsigned int type,

int gic_configure_irq(unsigned int irq, unsigned int type,

		       void __iomem *base, void (*sync_access)(void))

		       void __iomem *base, void (*sync_access)(void))

{

{

	u32 enablemask = 1 << (irq % 32);

	u32 enableoff = (irq / 32) * 4;

	u32 confmask = 0x2 << ((irq % 16) * 2);

	u32 confmask = 0x2 << ((irq % 16) * 2);

	u32 confoff = (irq / 16) * 4;

	u32 confoff = (irq / 16) * 4;

	bool enabled = false;

	u32 val, oldval;

	u32 val, oldval;

	int ret = 0;

	int ret = 0;
@@ -42,17 +39,6 @@ int gic_configure_irq(unsigned int irq, unsigned int type, 
	else if (type & IRQ_TYPE_EDGE_BOTH)

	else if (type & IRQ_TYPE_EDGE_BOTH)

		val |= confmask;

		val |= confmask;





	/*

	 * As recommended by the spec, disable the interrupt before changing

	 * the configuration

	 */

	if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {

		writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);

		if (sync_access)

			sync_access();

		enabled = true;

	}



	/*

	/*

	 * Write back the new configuration, and possibly re-enable

	 * Write back the new configuration, and possibly re-enable

	 * the interrupt. If we tried to write a new configuration and failed,

	 * the interrupt. If we tried to write a new configuration and failed,
@@ -62,9 +48,6 @@ int gic_configure_irq(unsigned int irq, unsigned int type, 
	if (readl_relaxed(base + GIC_DIST_CONFIG + confoff) != val && val != oldval)

	if (readl_relaxed(base + GIC_DIST_CONFIG + confoff) != val && val != oldval)

		ret = -EINVAL;

		ret = -EINVAL;





	if (enabled)

		writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);



	if (sync_access)

	if (sync_access)

		sync_access();

		sync_access();

drivers/irqchip/irq-gic-v3.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -658,6 +658,7 @@ static struct irq_chip gic_chip = { 
	.irq_set_affinity	= gic_set_affinity,

	.irq_set_affinity	= gic_set_affinity,

	.irq_get_irqchip_state	= gic_irq_get_irqchip_state,

	.irq_get_irqchip_state	= gic_irq_get_irqchip_state,

	.irq_set_irqchip_state	= gic_irq_set_irqchip_state,

	.irq_set_irqchip_state	= gic_irq_set_irqchip_state,

	.flags			= IRQCHIP_SET_TYPE_MASKED,

};

};





#define GIC_ID_NR		(1U << gic_data.rdists.id_bits)

#define GIC_ID_NR		(1U << gic_data.rdists.id_bits)

drivers/irqchip/irq-gic.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -324,6 +324,7 @@ static struct irq_chip gic_chip = { 
#endif

#endif

	.irq_get_irqchip_state	= gic_irq_get_irqchip_state,

	.irq_get_irqchip_state	= gic_irq_get_irqchip_state,

	.irq_set_irqchip_state	= gic_irq_set_irqchip_state,

	.irq_set_irqchip_state	= gic_irq_set_irqchip_state,

	.flags			= IRQCHIP_SET_TYPE_MASKED,

};

};





void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)

void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)

drivers/irqchip/irq-hip04.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -202,6 +202,7 @@ static struct irq_chip hip04_irq_chip = { 
#ifdef CONFIG_SMP

#ifdef CONFIG_SMP

	.irq_set_affinity	= hip04_irq_set_affinity,

	.irq_set_affinity	= hip04_irq_set_affinity,

#endif

#endif

	.flags			= IRQCHIP_SET_TYPE_MASKED,

};

};





static u16 hip04_get_cpumask(struct hip04_irq_data *intc)

static u16 hip04_get_cpumask(struct hip04_irq_data *intc)