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Commit 5524a67f authored by Wolfram Sang's avatar Wolfram Sang Committed by Geert Uytterhoeven
Browse files

clk: renesas: r8a7795: add OSC and RINT clocks 



Signed-off-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 5d3927f6

drivers/clk/renesas/r8a7795-cpg-mssr.c

+5 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 


#include "renesas-cpg-mssr.h"



#define CPG_RCKCR	0x240



enum clk_ids {

	/* Core Clock Outputs exported to DT */
@@ -50,6 +51,7 @@ enum clk_ids { 
	CLK_S3,

	CLK_SDSRC,

	CLK_SSPSRC,

	CLK_RINT,



	/* Module Clocks */

	MOD_CLK_BASE
@@ -116,6 +118,9 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = { 
	DEF_DIV6P1("mso",       R8A7795_CLK_MSO,   CLK_PLL1_DIV4, 0x014),

	DEF_DIV6P1("hdmi",      R8A7795_CLK_HDMI,  CLK_PLL1_DIV2, 0x250),

	DEF_DIV6P1("canfd",     R8A7795_CLK_CANFD, CLK_PLL1_DIV4, 0x244),



	DEF_DIV6_RO("osc",      R8A7795_CLK_OSC,   CLK_EXTAL, CPG_RCKCR, 8),

	DEF_DIV6_RO("r_int",    CLK_RINT,          CLK_EXTAL, CPG_RCKCR, 32),

};



static const struct mssr_mod_clk r8a7795_mod_clks[] __initconst = {