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Commit 551266c9 authored by Maya Erez's avatar Maya Erez
Browse files

wil6210: configure OTP HW vectors in SW reset flow 



OTP HW vectors values are different for 40MHz and 330MHz AHB
clocks.
In SW reset flow, the host driver sets the clock frequency
to 40MHz. In order to allow reading from the OTP, the host
driver should configure the OTP HW vectors with the values
that fits this clock frequency.

Change-Id: I4fc847533fe89f8ddf960af2b5a6ff1b55d03b00
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
Git-commit: b8e13b87b15d2dde8c61ad7de5626d07a9d4da01
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git


Signed-off-by: default avatarMaya Erez <merez@codeaurora.org>
parent c1d0d3e3

drivers/net/wireless/ath/wil6210/main.c

+15 −0
Original line number Diff line number Diff line
@@ -769,6 +769,21 @@ static int wil_target_reset(struct wil6210_priv *wil, int no_flash) 
	wil_s(wil, RGF_DMA_OFUL_NID_0, BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN |

	      BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC);



	if (no_flash) {

		/* Reset OTP HW vectors to fit 40MHz */

		wil_w(wil, RGF_USER_XPM_IFC_RD_TIME1, 0x60001);

		wil_w(wil, RGF_USER_XPM_IFC_RD_TIME2, 0x20027);

		wil_w(wil, RGF_USER_XPM_IFC_RD_TIME3, 0x1);

		wil_w(wil, RGF_USER_XPM_IFC_RD_TIME4, 0x20027);

		wil_w(wil, RGF_USER_XPM_IFC_RD_TIME5, 0x30003);

		wil_w(wil, RGF_USER_XPM_IFC_RD_TIME6, 0x20002);

		wil_w(wil, RGF_USER_XPM_IFC_RD_TIME7, 0x60001);

		wil_w(wil, RGF_USER_XPM_IFC_RD_TIME8, 0x60001);

		wil_w(wil, RGF_USER_XPM_IFC_RD_TIME9, 0x60001);

		wil_w(wil, RGF_USER_XPM_IFC_RD_TIME10, 0x60001);

		wil_w(wil, RGF_USER_XPM_RD_DOUT_SAMPLE_TIME, 0x57);

	}



	wil_dbg_misc(wil, "Reset completed in %d ms\n", delay * RST_DELAY);

	return 0;

}

drivers/net/wireless/ath/wil6210/wil6210.h

+11 −0
Original line number Diff line number Diff line
@@ -198,6 +198,17 @@ struct RGF_ICR { 
	#define BIT_SPARROW_M_4_SEL_SLEEP_OR_REF	BIT(2)

#define RGF_USER_OTP_HW_RD_MACHINE_1	(0x880ce0)

	#define BIT_NO_FLASH_INDICATION		BIT(8)

#define RGF_USER_XPM_IFC_RD_TIME1	(0x880cec)

#define RGF_USER_XPM_IFC_RD_TIME2	(0x880cf0)

#define RGF_USER_XPM_IFC_RD_TIME3	(0x880cf4)

#define RGF_USER_XPM_IFC_RD_TIME4	(0x880cf8)

#define RGF_USER_XPM_IFC_RD_TIME5	(0x880cfc)

#define RGF_USER_XPM_IFC_RD_TIME6	(0x880d00)

#define RGF_USER_XPM_IFC_RD_TIME7	(0x880d04)

#define RGF_USER_XPM_IFC_RD_TIME8	(0x880d08)

#define RGF_USER_XPM_IFC_RD_TIME9	(0x880d0c)

#define RGF_USER_XPM_IFC_RD_TIME10	(0x880d10)

#define RGF_USER_XPM_RD_DOUT_SAMPLE_TIME (0x880d64)



#define RGF_DMA_EP_TX_ICR		(0x881bb4) /* struct RGF_ICR */

	#define BIT_DMA_EP_TX_ICR_TX_DONE	BIT(0)