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Commit 54b33352 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus 

* 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus: (28 commits)
  MIPS: Alchemy: fix xxs1500 build error
  MIPS: Invalidate old TLB mappings when updating huge page PTEs.
  MIPS: Hibernation: Fixes for PAGE_SIZE >= 64kb
  MIPS: JZ4740: Set one-shot feature flag for the clockevent
  MIPS: JZ4740: Export symbols to the watchdog driver module
  MIPS: JZ4740: Fix GCC 4.6.0 build error.
  MIPS: Audit: Fix success success argument pass to audit_syscall_exit
  MIPS: Fix calc_vmlinuz_load_addr build warnings.
  MIPS: Alchemy: Fix GCC 4.6.0 build error.
  MIPS: Document former use of timerfd(2) syscall number.
  MIPS: IP27: Fix GCC 4.6.0 build error.
  MIPS: IP27: Fix GCC 4.6.0 build error.
  MIPS: bcm63xx: Fix header_crc comment in bcm963xx_tag.h
  MIPS: Octeon: Guard the Kconfig body with CPU_CAVIUM_OCTEON
  MIPS: Octeon: Cleanup Kconfig IRQ_CPU* symbols.
  MIPS: Rename .data..mostly and properly handle it in linker script
  MIPS: MSP: Fix build error
  MIPS: MSP71xx: Fix typo in msp_per_irq_controller
  MIPS: Loongson: Fix GCC 2.6.0 build error.
  MIPS: Jazz: Fix GCC 4.6.0 build error
  ...
parents 675badfc 780914c3

arch/mips/Kconfig

+0 −5
Original line number Diff line number Diff line
@@ -997,9 +997,6 @@ config IRQ_GT641XX 
config IRQ_GIC

	bool



config IRQ_CPU_OCTEON

	bool



config MIPS_BOARDS_GEN

	bool
@@ -1359,8 +1356,6 @@ config CPU_SB1 
config CPU_CAVIUM_OCTEON

	bool "Cavium Octeon processor"

	depends on SYS_HAS_CPU_CAVIUM_OCTEON

	select IRQ_CPU

	select IRQ_CPU_OCTEON

	select CPU_HAS_PREFETCH

	select CPU_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_SMP

arch/mips/alchemy/devboards/db1x00/board_setup.c

+33 −28
Original line number Diff line number Diff line
@@ -127,13 +127,10 @@ const char *get_system_type(void) 
void __init board_setup(void)

{

	unsigned long bcsr1, bcsr2;

	u32 pin_func;



	bcsr1 = DB1000_BCSR_PHYS_ADDR;

	bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS;



	pin_func = 0;



#ifdef CONFIG_MIPS_DB1000

	printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n");

#endif
@@ -164,12 +161,16 @@ void __init board_setup(void) 
	/* Not valid for Au1550 */

#if defined(CONFIG_IRDA) && \

   (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100))

	{

		u32 pin_func;



		/* Set IRFIRSEL instead of GPIO15 */

		pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF;

		au_writel(pin_func, SYS_PINFUNC);

		/* Power off until the driver is in use */

		bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK,

			 BCSR_RESETS_IRDA_MODE_OFF);

	}

#endif

	bcsr_write(BCSR_PCMCIA, 0);	/* turn off PCMCIA power */
@@ -177,6 +178,9 @@ void __init board_setup(void) 
	alchemy_gpio1_input_enable();



#ifdef CONFIG_MIPS_MIRAGE

	{

		u32 pin_func;



		/* GPIO[20] is output */

		alchemy_gpio_direction_output(20, 0);
@@ -202,6 +206,7 @@ void __init board_setup(void) 
		pm_power_off = mirage_power_off;

		_machine_halt = mirage_power_off;

		_machine_restart = (void(*)(char *))mips_softreset;

	}

#endif



#ifdef CONFIG_MIPS_BOSPORUS

arch/mips/alchemy/xxs1500/init.c

+2 −3
Original line number Diff line number Diff line
@@ -51,10 +51,9 @@ void __init prom_init(void) 
	prom_init_cmdline();



	memsize_str = prom_getenv("memsize");

	if (!memsize_str)

	if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize))

		memsize = 0x04000000;

	else

		strict_strtoul(memsize_str, 0, &memsize);



	add_memory_region(0, memsize, BOOT_MEM_RAM);

}

arch/mips/boot/compressed/calc_vmlinuz_load_addr.c

+1 −1
Original line number Diff line number Diff line
@@ -16,8 +16,8 @@ 


int main(int argc, char *argv[])

{

	unsigned long long vmlinux_size, vmlinux_load_addr, vmlinuz_load_addr;

	struct stat sb;

	uint64_t vmlinux_size, vmlinux_load_addr, vmlinuz_load_addr;



	if (argc != 3) {

		fprintf(stderr, "Usage: %s <pathname> <vmlinux_load_addr>\n",

arch/mips/cavium-octeon/Kconfig

+4 −11
Original line number Diff line number Diff line 
config CAVIUM_OCTEON_SPECIFIC_OPTIONS

	bool "Enable Octeon specific options"

	depends on CPU_CAVIUM_OCTEON

	default "y"

if CPU_CAVIUM_OCTEON



config CAVIUM_CN63XXP1

	bool "Enable CN63XXP1 errata worarounds"

	depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS

	default "n"

	help

	  The CN63XXP1 chip requires build time workarounds to
@@ -16,7 +12,6 @@ config CAVIUM_CN63XXP1 


config CAVIUM_OCTEON_2ND_KERNEL

	bool "Build the kernel to be used as a 2nd kernel on the same chip"

	depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS

	default "n"

	help

	  This option configures this kernel to be linked at a different
@@ -26,7 +21,6 @@ config CAVIUM_OCTEON_2ND_KERNEL 


config CAVIUM_OCTEON_HW_FIX_UNALIGNED

	bool "Enable hardware fixups of unaligned loads and stores"

	depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS

	default "y"

	help

	  Configure the Octeon hardware to automatically fix unaligned loads
@@ -38,7 +32,6 @@ config CAVIUM_OCTEON_HW_FIX_UNALIGNED 


config CAVIUM_OCTEON_CVMSEG_SIZE

	int "Number of L1 cache lines reserved for CVMSEG memory"

	depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS

	range 0 54

	default 1

	help
@@ -50,7 +43,6 @@ config CAVIUM_OCTEON_CVMSEG_SIZE 


config CAVIUM_OCTEON_LOCK_L2

	bool "Lock often used kernel code in the L2"

	depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS

	default "y"

	help

	  Enable locking parts of the kernel into the L2 cache.
@@ -93,7 +85,6 @@ config CAVIUM_OCTEON_LOCK_L2_MEMCPY 
config ARCH_SPARSEMEM_ENABLE

	def_bool y

	select SPARSEMEM_STATIC

	depends on CPU_CAVIUM_OCTEON



config CAVIUM_OCTEON_HELPER

	def_bool y
@@ -107,6 +98,8 @@ config NEED_SG_DMA_LENGTH 


config SWIOTLB

	def_bool y

	depends on CPU_CAVIUM_OCTEON

	select IOMMU_HELPER

	select NEED_SG_DMA_LENGTH





endif # CPU_CAVIUM_OCTEON