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Commit 549f3ae1 authored by Pratyush Anand's avatar Pratyush Anand Committed by Viresh Kumar
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ARM: SPEAr13xx: Add pcie and miphy DT nodes 



This patch adds necessary DT nodes for pcie controllers and miphys for SPEAr13xx
SoCs.

SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed with
ahci/sata pins. By default evaluation board of both controller works in ahci
mode. Because of this, these nodes are marked "disabled" by default.

In order to use pcie controller on evaluation boards do necessary modifications
on board and enable (By replacing "disabled" with "okay") pcie and miphy from
respective 'evb' dtsi file.

Phy specific initialization was previously done from spear1340.c, which isn't
required anymore as we have separate drivers for it. Remove it.

Acked-by: default avatarArnd Bergmann <arnd@arndb.de>
Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: default avatarPratyush Anand <pratyush.anand@st.com>
Signed-off-by: default avatarMohit Kumar <mohit.kumar@st.com>
[viresh: fixed logs/cclist/checkpatch warnings, clubbed multiple patches into one]
Signed-off-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
parent 23b7ad23

arch/arm/boot/dts/spear1310-evb.dts

+4 −0
Original line number Diff line number Diff line
@@ -106,6 +106,10 @@ 
			status = "okay";

		};



		miphy@eb800000 {

			status = "okay";

		};



		cf@b2800000 {

			status = "okay";

		};

arch/arm/boot/dts/spear1310.dtsi

+90 −3
Original line number Diff line number Diff line
@@ -29,24 +29,111 @@ 
			#gpio-cells = <2>;

		};



		ahci@b1000000 {

		miphy0: miphy@eb800000 {

			compatible = "st,spear1310-miphy";

			reg = <0xeb800000 0x4000>;

			misc = <&misc>;

			phy-id = <0>;

			#phy-cells = <1>;

			status = "disabled";

		};



		miphy1: miphy@eb804000 {

			compatible = "st,spear1310-miphy";

			reg = <0xeb804000 0x4000>;

			misc = <&misc>;

			phy-id = <1>;

			#phy-cells = <1>;

			status = "disabled";

		};



		miphy2: miphy@eb808000 {

			compatible = "st,spear1310-miphy";

			reg = <0xeb808000 0x4000>;

			misc = <&misc>;

			phy-id = <2>;

			#phy-cells = <1>;

			status = "disabled";

		};



		ahci0: ahci@b1000000 {

			compatible = "snps,spear-ahci";

			reg = <0xb1000000 0x10000>;

			interrupts = <0 68 0x4>;

			phys = <&miphy0 0>;

			phy-names = "sata-phy";

			status = "disabled";

		};



		ahci@b1800000 {

		ahci1: ahci@b1800000 {

			compatible = "snps,spear-ahci";

			reg = <0xb1800000 0x10000>;

			interrupts = <0 69 0x4>;

			phys = <&miphy1 0>;

			phy-names = "sata-phy";

			status = "disabled";

		};



		ahci@b4000000 {

		ahci2: ahci@b4000000 {

			compatible = "snps,spear-ahci";

			reg = <0xb4000000 0x10000>;

			interrupts = <0 70 0x4>;

			phys = <&miphy2 0>;

			phy-names = "sata-phy";

			status = "disabled";

		};



		pcie0: pcie@b1000000 {

			compatible = "st,spear1340-pcie", "snps,dw-pcie";

			reg = <0xb1000000 0x4000>;

			interrupts = <0 68 0x4>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0x0 0 &gic 0 68 0x4>;

			num-lanes = <1>;

			phys = <&miphy0 1>;

			phy-names = "pcie-phy";

			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";

			ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000   /* configuration space */

				0x81000000 0 0	 0x80020000 0 0x00010000   /* downstream I/O */

				0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */

			status = "disabled";

		};



		pcie1: pcie@b1800000 {

			compatible = "st,spear1340-pcie", "snps,dw-pcie";

			reg = <0xb1800000 0x4000>;

			interrupts = <0 69 0x4>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0x0 0 &gic 0 69 0x4>;

			num-lanes = <1>;

			phys = <&miphy1 1>;

			phy-names = "pcie-phy";

			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";

			ranges = <0x00000800 0 0x90000000 0x90000000 0 0x00020000   /* configuration space */

				0x81000000 0 0  0x90020000 0 0x00010000   /* downstream I/O */

				0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */

			status = "disabled";

		};



		pcie2: pcie@b4000000 {

			compatible = "st,spear1340-pcie", "snps,dw-pcie";

			reg = <0xb4000000 0x4000>;

			interrupts = <0 70 0x4>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0x0 0 &gic 0 70 0x4>;

			num-lanes = <1>;

			phys = <&miphy2 1>;

			phy-names = "pcie-phy";

			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";

			ranges = <0x00000800 0 0xc0000000 0xc0000000 0 0x00020000   /* configuration space */

				0x81000000 0 0	 0xc0020000 0 0x00010000   /* downstream I/O */

				0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */

			status = "disabled";

		};

arch/arm/boot/dts/spear1340-evb.dts

+4 −0
Original line number Diff line number Diff line
@@ -122,6 +122,10 @@ 
			status = "okay";

		};



		miphy@eb800000 {

			status = "okay";

		};



		dma@ea800000 {

			status = "okay";

		};

arch/arm/boot/dts/spear1340.dtsi

+29 −1
Original line number Diff line number Diff line
@@ -31,10 +31,38 @@ 
			status = "disabled";

		};



		ahci@b1000000 {

		miphy0: miphy@eb800000 {

			compatible = "st,spear1340-miphy";

			reg = <0xeb800000 0x4000>;

			misc = <&misc>;

			#phy-cells = <1>;

			status = "disabled";

		};



		ahci0: ahci@b1000000 {

			compatible = "snps,spear-ahci";

			reg = <0xb1000000 0x10000>;

			interrupts = <0 72 0x4>;

			phys = <&miphy0 0>;

			phy-names = "sata-phy";

			status = "disabled";

		};



		pcie0: pcie@b1000000 {

			compatible = "st,spear1340-pcie", "snps,dw-pcie";

			reg = <0xb1000000 0x4000>;

			interrupts = <0 68 0x4>;

			interrupt-map-mask = <0 0 0 0>;

			interrupt-map = <0x0 0 &gic 0 68 0x4>;

			num-lanes = <1>;

			phys = <&miphy0 1>;

			phy-names = "pcie-phy";

			#address-cells = <3>;

			#size-cells = <2>;

			device_type = "pci";

			ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000   /* configuration space */

				0x81000000 0 0	 0x80020000 0 0x00010000   /* downstream I/O */

				0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */

			status = "disabled";

		};

arch/arm/boot/dts/spear13xx.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -83,8 +83,8 @@ 
		#size-cells = <1>;

		compatible = "simple-bus";

		ranges = <0x50000000 0x50000000 0x10000000

			  0xb0000000 0xb0000000 0x10000000

			  0xd0000000 0xd0000000 0x02000000

			  0x80000000 0x80000000 0x20000000

			  0xb0000000 0xb0000000 0x22000000

			  0xd8000000 0xd8000000 0x01000000

			  0xe0000000 0xe0000000 0x10000000>;