Loading arch/arm64/boot/dts/qcom/sdm845.dtsi +52 −0 Original line number Diff line number Diff line Loading @@ -500,6 +500,58 @@ cell-index = <0>; }; msm_cpufreq: qcom,msm-cpufreq { compatible = "qcom,msm-cpufreq"; clock-names = "cpu0_clk", "cpu4_clk"; clocks = <&clock_cpucc CPU0_PWRCL_CLK>, <&clock_cpucc CPU4_PERFCL_CLK>; qcom,governor-per-policy; qcom,cpufreq-table-0 = < 300000 >, < 422400 >, < 499200 >, < 576000 >, < 652800 >, < 748800 >, < 825600 >, < 902400 >, < 979200 >, < 1056000 >, < 1132800 >, < 1209600 >, < 1286400 >, < 1363200 >, < 1440000 >, < 1516800 >, < 1593600 >; qcom,cpufreq-table-4 = < 300000 >, < 422400 >, < 499200 >, < 576000 >, < 652800 >, < 729600 >, < 806400 >, < 883200 >, < 960000 >, < 1036800 >, < 1113600 >, < 1190400 >, < 1267200 >, < 1344000 >, < 1420800 >, < 1497600 >, < 1574400 >, < 1651200 >, < 1728000 >, < 1804800 >, < 1881600 >, < 1958400 >; }; clock_gcc: qcom,gcc@100000 { compatible = "qcom,gcc-sdm845"; reg = <0x100000 0x1f0000>; Loading Loading
arch/arm64/boot/dts/qcom/sdm845.dtsi +52 −0 Original line number Diff line number Diff line Loading @@ -500,6 +500,58 @@ cell-index = <0>; }; msm_cpufreq: qcom,msm-cpufreq { compatible = "qcom,msm-cpufreq"; clock-names = "cpu0_clk", "cpu4_clk"; clocks = <&clock_cpucc CPU0_PWRCL_CLK>, <&clock_cpucc CPU4_PERFCL_CLK>; qcom,governor-per-policy; qcom,cpufreq-table-0 = < 300000 >, < 422400 >, < 499200 >, < 576000 >, < 652800 >, < 748800 >, < 825600 >, < 902400 >, < 979200 >, < 1056000 >, < 1132800 >, < 1209600 >, < 1286400 >, < 1363200 >, < 1440000 >, < 1516800 >, < 1593600 >; qcom,cpufreq-table-4 = < 300000 >, < 422400 >, < 499200 >, < 576000 >, < 652800 >, < 729600 >, < 806400 >, < 883200 >, < 960000 >, < 1036800 >, < 1113600 >, < 1190400 >, < 1267200 >, < 1344000 >, < 1420800 >, < 1497600 >, < 1574400 >, < 1651200 >, < 1728000 >, < 1804800 >, < 1881600 >, < 1958400 >; }; clock_gcc: qcom,gcc@100000 { compatible = "qcom,gcc-sdm845"; reg = <0x100000 0x1f0000>; Loading