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Commit 544c7805 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: Add voter clocks for gcc_aggre_ufs_phy_axi_clk for SDM670"

parents 6b22e71e 1cf767ae

drivers/clk/qcom/common.c

+21 −2
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2013-2014, 2017, The Linux Foundation. All rights reserved.

 * Copyright (c) 2013-2014, 2017-2018,

 * The Linux Foundation. All rights reserved.

 *

 * This software is licensed under the terms of the GNU General Public

 * License version 2, as published by the Free Software Foundation, and
@@ -30,7 +31,9 @@ 
struct qcom_cc {

	struct qcom_reset_controller reset;

	struct clk_regmap **rclks;

	struct clk_hw **hwclks;

	size_t num_rclks;

	size_t num_hwclks;

};



const
@@ -182,11 +185,14 @@ static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec, 
	struct qcom_cc *cc = data;

	unsigned int idx = clkspec->args[0];



	if (idx >= cc->num_rclks) {

	if (idx >= cc->num_rclks + cc->num_hwclks) {

		pr_err("invalid index %u\n", idx);

		return ERR_PTR(-EINVAL);

	}



	if (idx < cc->num_hwclks && cc->hwclks[idx])

		return cc->hwclks[idx];



	return cc->rclks[idx] ? &cc->rclks[idx]->hw : ERR_PTR(-ENOENT);

}
@@ -199,7 +205,9 @@ int qcom_cc_really_probe(struct platform_device *pdev, 
	struct qcom_cc *cc;

	struct gdsc_desc *scd;

	size_t num_clks = desc->num_clks;

	size_t num_hwclks = desc->num_hwclks;

	struct clk_regmap **rclks = desc->clks;

	struct clk_hw **hwclks = desc->hwclks;



	cc = devm_kzalloc(dev, sizeof(*cc), GFP_KERNEL);

	if (!cc)
@@ -207,6 +215,17 @@ int qcom_cc_really_probe(struct platform_device *pdev, 


	cc->rclks = rclks;

	cc->num_rclks = num_clks;

	cc->hwclks = hwclks;

	cc->num_hwclks = num_hwclks;



	for (i = 0; i < num_hwclks; i++) {

		if (!hwclks[i])

			continue;



		ret = devm_clk_hw_register(dev, hwclks[i]);

		if (ret)

			return ret;

	}



	for (i = 0; i < num_clks; i++) {

		if (!rclks[i])

drivers/clk/qcom/common.h

+3 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.

 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.

 *

 * This software is licensed under the terms of the GNU General Public

 * License version 2, as published by the Free Software Foundation, and
@@ -28,7 +28,9 @@ struct parent_map; 
struct qcom_cc_desc {

	const struct regmap_config *config;

	struct clk_regmap **clks;

	struct clk_hw **hwclks;

	size_t num_clks;

	size_t num_hwclks;

	const struct qcom_reset_map *resets;

	size_t num_resets;

	struct gdsc **gdscs;

drivers/clk/qcom/gcc-sdm845.c

+12 −10
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -35,6 +35,7 @@ 
#include "reset.h"

#include "clk-alpha-pll.h"

#include "vdd-level-sdm845.h"

#include "clk-voter.h"



#define GCC_MMSS_MISC				0x09FFC

#define GCC_GPU_MISC				0x71028
@@ -1505,6 +1506,11 @@ static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { 
	},

};



static DEFINE_CLK_VOTER(ufs_phy_axi_emmc_vote_clk,

					gcc_aggre_ufs_phy_axi_clk, 0);

static DEFINE_CLK_VOTER(ufs_phy_axi_ufs_vote_clk,

					gcc_aggre_ufs_phy_axi_clk, 0);



static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {

	.halt_reg = 0x82024,

	.clkr = {
@@ -3780,6 +3786,8 @@ struct clk_hw *gcc_sdm845_hws[] = { 
	[MEASURE_ONLY_CNOC_CLK] = &measure_only_cnoc_clk.hw,

	[MEASURE_ONLY_BIMC_CLK] = &measure_only_bimc_clk.hw,

	[MEASURE_ONLY_IPA_2X_CLK] = &measure_only_ipa_2x_clk.hw,

	[UFS_PHY_AXI_EMMC_VOTE_CLK] = &ufs_phy_axi_emmc_vote_clk.hw,

	[UFS_PHY_AXI_UFS_VOTE_CLK] = &ufs_phy_axi_ufs_vote_clk.hw,

};



static struct clk_regmap *gcc_sdm845_clocks[] = {
@@ -4061,6 +4069,8 @@ static const struct qcom_cc_desc gcc_sdm845_desc = { 
	.config = &gcc_sdm845_regmap_config,

	.clks = gcc_sdm845_clocks,

	.num_clks = ARRAY_SIZE(gcc_sdm845_clocks),

	.hwclks = gcc_sdm845_hws,

	.num_hwclks = ARRAY_SIZE(gcc_sdm845_hws),

	.resets = gcc_sdm845_resets,

	.num_resets = ARRAY_SIZE(gcc_sdm845_resets),

};
@@ -4279,9 +4289,8 @@ static int gcc_sdm845_fixup(struct platform_device *pdev) 


static int gcc_sdm845_probe(struct platform_device *pdev)

{

	struct clk *clk;

	struct regmap *regmap;

	int i, ret = 0;

	int ret = 0;



	regmap = qcom_cc_map(pdev, &gcc_sdm845_desc);

	if (IS_ERR(regmap))
@@ -4307,13 +4316,6 @@ static int gcc_sdm845_probe(struct platform_device *pdev) 
	if (ret)

		return ret;



	/* Register the dummy measurement clocks */

	for (i = 0; i < ARRAY_SIZE(gcc_sdm845_hws); i++) {

		clk = devm_clk_register(&pdev->dev, gcc_sdm845_hws[i]);

		if (IS_ERR(clk))

			return PTR_ERR(clk);

	}



	ret = qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap);

	if (ret) {

		dev_err(&pdev->dev, "Failed to register GCC clocks\n");

include/dt-bindings/clock/qcom,gcc-sdm845.h

+207 −205
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -14,205 +14,213 @@ 
#ifndef _DT_BINDINGS_CLK_MSM_GCC_SDM845_H

#define _DT_BINDINGS_CLK_MSM_GCC_SDM845_H



/* Dummy clocks for rate measurement */

#define MEASURE_ONLY_SNOC_CLK					0

#define MEASURE_ONLY_CNOC_CLK					1

#define MEASURE_ONLY_BIMC_CLK					2

#define MEASURE_ONLY_IPA_2X_CLK					3

#define UFS_PHY_AXI_EMMC_VOTE_CLK				4

#define UFS_PHY_AXI_UFS_VOTE_CLK				5



/* GCC clock registers */

#define GCC_AGGRE_NOC_PCIE_TBU_CLK				0

#define GCC_AGGRE_UFS_CARD_AXI_CLK				1

#define GCC_AGGRE_UFS_PHY_AXI_CLK				2

#define GCC_AGGRE_USB3_PRIM_AXI_CLK				3

#define GCC_AGGRE_USB3_SEC_AXI_CLK				4

#define GCC_BOOT_ROM_AHB_CLK					5

#define GCC_CAMERA_AHB_CLK					6

#define GCC_CAMERA_AXI_CLK					7

#define GCC_CAMERA_XO_CLK					8

#define GCC_CE1_AHB_CLK						9

#define GCC_CE1_AXI_CLK						10

#define GCC_CE1_CLK						11

#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				12

#define GCC_CFG_NOC_USB3_SEC_AXI_CLK				13

#define GCC_CPUSS_AHB_CLK					14

#define GCC_CPUSS_AHB_CLK_SRC					15

#define GCC_CPUSS_DVM_BUS_CLK					16

#define GCC_CPUSS_GNOC_CLK					17

#define GCC_CPUSS_RBCPR_CLK					18

#define GCC_CPUSS_RBCPR_CLK_SRC					19

#define GCC_DDRSS_GPU_AXI_CLK					20

#define GCC_DISP_AHB_CLK					21

#define GCC_DISP_AXI_CLK					22

#define GCC_DISP_GPLL0_CLK_SRC					23

#define GCC_DISP_GPLL0_DIV_CLK_SRC				24

#define GCC_DISP_XO_CLK						25

#define GCC_GP1_CLK						26

#define GCC_GP1_CLK_SRC						27

#define GCC_GP2_CLK						28

#define GCC_GP2_CLK_SRC						29

#define GCC_GP3_CLK						30

#define GCC_GP3_CLK_SRC						31

#define GCC_GPU_CFG_AHB_CLK					32

#define GCC_GPU_GPLL0_CLK_SRC					33

#define GCC_GPU_GPLL0_DIV_CLK_SRC				34

#define GCC_GPU_MEMNOC_GFX_CLK					35

#define GCC_GPU_SNOC_DVM_GFX_CLK				36

#define GCC_MSS_AXIS2_CLK					37

#define GCC_MSS_CFG_AHB_CLK					38

#define GCC_MSS_GPLL0_DIV_CLK_SRC				39

#define GCC_MSS_MFAB_AXIS_CLK					40

#define GCC_MSS_Q6_MEMNOC_AXI_CLK				41

#define GCC_MSS_SNOC_AXI_CLK					42

#define GCC_PCIE_0_AUX_CLK					43

#define GCC_PCIE_0_AUX_CLK_SRC					44

#define GCC_PCIE_0_CFG_AHB_CLK					45

#define GCC_PCIE_0_CLKREF_CLK					46

#define GCC_PCIE_0_MSTR_AXI_CLK					47

#define GCC_PCIE_0_PIPE_CLK					48

#define GCC_PCIE_0_SLV_AXI_CLK					49

#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				50

#define GCC_PCIE_1_AUX_CLK					51

#define GCC_PCIE_1_AUX_CLK_SRC					52

#define GCC_PCIE_1_CFG_AHB_CLK					53

#define GCC_PCIE_1_CLKREF_CLK					54

#define GCC_PCIE_1_MSTR_AXI_CLK					55

#define GCC_PCIE_1_PIPE_CLK					56

#define GCC_PCIE_1_SLV_AXI_CLK					57

#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				58

#define GCC_PCIE_PHY_AUX_CLK					59

#define GCC_PCIE_PHY_REFGEN_CLK					60

#define GCC_PCIE_PHY_REFGEN_CLK_SRC				61

#define GCC_PDM2_CLK						62

#define GCC_PDM2_CLK_SRC					63

#define GCC_PDM_AHB_CLK						64

#define GCC_PDM_XO4_CLK						65

#define GCC_PRNG_AHB_CLK					66

#define GCC_QMIP_CAMERA_AHB_CLK					67

#define GCC_QMIP_DISP_AHB_CLK					68

#define GCC_QMIP_VIDEO_AHB_CLK					69

#define GCC_QUPV3_WRAP0_S0_CLK					70

#define GCC_QUPV3_WRAP0_S0_CLK_SRC				71

#define GCC_QUPV3_WRAP0_S1_CLK					72

#define GCC_QUPV3_WRAP0_S1_CLK_SRC				73

#define GCC_QUPV3_WRAP0_S2_CLK					74

#define GCC_QUPV3_WRAP0_S2_CLK_SRC				75

#define GCC_QUPV3_WRAP0_S3_CLK					76

#define GCC_QUPV3_WRAP0_S3_CLK_SRC				77

#define GCC_QUPV3_WRAP0_S4_CLK					78

#define GCC_QUPV3_WRAP0_S4_CLK_SRC				79

#define GCC_QUPV3_WRAP0_S5_CLK					80

#define GCC_QUPV3_WRAP0_S5_CLK_SRC				81

#define GCC_QUPV3_WRAP0_S6_CLK					82

#define GCC_QUPV3_WRAP0_S6_CLK_SRC				83

#define GCC_QUPV3_WRAP0_S7_CLK					84

#define GCC_QUPV3_WRAP0_S7_CLK_SRC				85

#define GCC_QUPV3_WRAP1_S0_CLK					86

#define GCC_QUPV3_WRAP1_S0_CLK_SRC				87

#define GCC_QUPV3_WRAP1_S1_CLK					88

#define GCC_QUPV3_WRAP1_S1_CLK_SRC				89

#define GCC_QUPV3_WRAP1_S2_CLK					90

#define GCC_QUPV3_WRAP1_S2_CLK_SRC				91

#define GCC_QUPV3_WRAP1_S3_CLK					92

#define GCC_QUPV3_WRAP1_S3_CLK_SRC				93

#define GCC_QUPV3_WRAP1_S4_CLK					94

#define GCC_QUPV3_WRAP1_S4_CLK_SRC				95

#define GCC_QUPV3_WRAP1_S5_CLK					96

#define GCC_QUPV3_WRAP1_S5_CLK_SRC				97

#define GCC_QUPV3_WRAP1_S6_CLK					98

#define GCC_QUPV3_WRAP1_S6_CLK_SRC				99

#define GCC_QUPV3_WRAP1_S7_CLK					100

#define GCC_QUPV3_WRAP1_S7_CLK_SRC				101

#define GCC_QUPV3_WRAP_0_M_AHB_CLK				102

#define GCC_QUPV3_WRAP_0_S_AHB_CLK				103

#define GCC_QUPV3_WRAP_1_M_AHB_CLK				104

#define GCC_QUPV3_WRAP_1_S_AHB_CLK				105

#define GCC_SDCC2_AHB_CLK					106

#define GCC_SDCC2_APPS_CLK					107

#define GCC_SDCC2_APPS_CLK_SRC					108

#define GCC_SDCC4_AHB_CLK					109

#define GCC_SDCC4_APPS_CLK					110

#define GCC_SDCC4_APPS_CLK_SRC					111

#define GCC_SYS_NOC_CPUSS_AHB_CLK				112

#define GCC_TSIF_AHB_CLK					113

#define GCC_TSIF_INACTIVITY_TIMERS_CLK				114

#define GCC_TSIF_REF_CLK					115

#define GCC_TSIF_REF_CLK_SRC					116

#define GCC_UFS_CARD_AHB_CLK					117

#define GCC_UFS_CARD_AXI_CLK					118

#define GCC_UFS_CARD_AXI_CLK_SRC				119

#define GCC_UFS_CARD_CLKREF_CLK					120

#define GCC_UFS_CARD_ICE_CORE_CLK				121

#define GCC_UFS_CARD_ICE_CORE_CLK_SRC				122

#define GCC_UFS_CARD_PHY_AUX_CLK				123

#define GCC_UFS_CARD_PHY_AUX_CLK_SRC				124

#define GCC_UFS_CARD_RX_SYMBOL_0_CLK				125

#define GCC_UFS_CARD_RX_SYMBOL_1_CLK				126

#define GCC_UFS_CARD_TX_SYMBOL_0_CLK				127

#define GCC_UFS_CARD_UNIPRO_CORE_CLK				128

#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			129

#define GCC_UFS_MEM_CLKREF_CLK					130

#define GCC_UFS_PHY_AHB_CLK					131

#define GCC_UFS_PHY_AXI_CLK					132

#define GCC_UFS_PHY_AXI_CLK_SRC					133

#define GCC_UFS_PHY_ICE_CORE_CLK				134

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				135

#define GCC_UFS_PHY_PHY_AUX_CLK					136

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				137

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				138

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				139

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				140

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				141

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				142

#define GCC_USB30_PRIM_MASTER_CLK				143

#define GCC_USB30_PRIM_MASTER_CLK_SRC				144

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				145

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			146

#define GCC_USB30_PRIM_SLEEP_CLK				147

#define GCC_USB30_SEC_MASTER_CLK				148

#define GCC_USB30_SEC_MASTER_CLK_SRC				149

#define GCC_USB30_SEC_MOCK_UTMI_CLK				150

#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				151

#define GCC_USB30_SEC_SLEEP_CLK					152

#define GCC_USB3_PRIM_CLKREF_CLK				153

#define GCC_USB3_PRIM_PHY_AUX_CLK				154

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				155

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				156

#define GCC_USB3_PRIM_PHY_PIPE_CLK				157

#define GCC_USB3_SEC_CLKREF_CLK					158

#define GCC_USB3_SEC_PHY_AUX_CLK				159

#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				160

#define GCC_USB3_SEC_PHY_COM_AUX_CLK				161

#define GCC_USB3_SEC_PHY_PIPE_CLK				162

#define GCC_USB_PHY_CFG_AHB2PHY_CLK				163

#define GCC_VIDEO_AHB_CLK					164

#define GCC_VIDEO_AXI_CLK					165

#define GCC_VIDEO_XO_CLK					166

#define GPLL0							167

#define GPLL0_OUT_EVEN						168

#define GPLL0_OUT_MAIN						169

#define GCC_UFS_CARD_AXI_HW_CTL_CLK				170

#define GCC_UFS_PHY_AXI_HW_CTL_CLK				171

#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK			172

#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK			173

#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK			174

#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK				175

#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK			176

#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK			177

#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK				178

#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK				179

#define GCC_GPU_IREF_CLK					180

#define GCC_SDCC1_AHB_CLK					181

#define GCC_SDCC1_APPS_CLK					182

#define GCC_SDCC1_ICE_CORE_CLK					183

#define GCC_SDCC1_APPS_CLK_SRC					184

#define GCC_SDCC1_ICE_CORE_CLK_SRC				185

#define GCC_APC_VS_CLK						186

#define GCC_GPU_VS_CLK						187

#define GCC_MSS_VS_CLK						188

#define GCC_VDDA_VS_CLK						189

#define GCC_VDDCX_VS_CLK					190

#define GCC_VDDMX_VS_CLK					191

#define GCC_VS_CTRL_AHB_CLK					192

#define GCC_VS_CTRL_CLK						193

#define GCC_VS_CTRL_CLK_SRC					194

#define GCC_VSENSOR_CLK_SRC					195

#define GPLL4							196

#define GPLL6							197

#define GCC_AGGRE_NOC_PCIE_TBU_CLK				6

#define GCC_AGGRE_UFS_CARD_AXI_CLK				7

#define GCC_AGGRE_UFS_PHY_AXI_CLK				8

#define GCC_AGGRE_USB3_PRIM_AXI_CLK				9

#define GCC_AGGRE_USB3_SEC_AXI_CLK				10

#define GCC_BOOT_ROM_AHB_CLK					11

#define GCC_CAMERA_AHB_CLK					12

#define GCC_CAMERA_AXI_CLK					13

#define GCC_CAMERA_XO_CLK					14

#define GCC_CE1_AHB_CLK						15

#define GCC_CE1_AXI_CLK						16

#define GCC_CE1_CLK						17

#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				18

#define GCC_CFG_NOC_USB3_SEC_AXI_CLK				19

#define GCC_CPUSS_AHB_CLK					20

#define GCC_CPUSS_AHB_CLK_SRC					21

#define GCC_CPUSS_DVM_BUS_CLK					22

#define GCC_CPUSS_GNOC_CLK					23

#define GCC_CPUSS_RBCPR_CLK					24

#define GCC_CPUSS_RBCPR_CLK_SRC					25

#define GCC_DDRSS_GPU_AXI_CLK					26

#define GCC_DISP_AHB_CLK					27

#define GCC_DISP_AXI_CLK					28

#define GCC_DISP_GPLL0_CLK_SRC					29

#define GCC_DISP_GPLL0_DIV_CLK_SRC				30

#define GCC_DISP_XO_CLK						31

#define GCC_GP1_CLK						32

#define GCC_GP1_CLK_SRC						33

#define GCC_GP2_CLK						34

#define GCC_GP2_CLK_SRC						35

#define GCC_GP3_CLK						36

#define GCC_GP3_CLK_SRC						37

#define GCC_GPU_CFG_AHB_CLK					38

#define GCC_GPU_GPLL0_CLK_SRC					39

#define GCC_GPU_GPLL0_DIV_CLK_SRC				40

#define GCC_GPU_MEMNOC_GFX_CLK					41

#define GCC_GPU_SNOC_DVM_GFX_CLK				42

#define GCC_MSS_AXIS2_CLK					43

#define GCC_MSS_CFG_AHB_CLK					44

#define GCC_MSS_GPLL0_DIV_CLK_SRC				45

#define GCC_MSS_MFAB_AXIS_CLK					46

#define GCC_MSS_Q6_MEMNOC_AXI_CLK				47

#define GCC_MSS_SNOC_AXI_CLK					48

#define GCC_PCIE_0_AUX_CLK					49

#define GCC_PCIE_0_AUX_CLK_SRC					50

#define GCC_PCIE_0_CFG_AHB_CLK					51

#define GCC_PCIE_0_CLKREF_CLK					52

#define GCC_PCIE_0_MSTR_AXI_CLK					53

#define GCC_PCIE_0_PIPE_CLK					54

#define GCC_PCIE_0_SLV_AXI_CLK					55

#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				56

#define GCC_PCIE_1_AUX_CLK					57

#define GCC_PCIE_1_AUX_CLK_SRC					58

#define GCC_PCIE_1_CFG_AHB_CLK					59

#define GCC_PCIE_1_CLKREF_CLK					60

#define GCC_PCIE_1_MSTR_AXI_CLK					61

#define GCC_PCIE_1_PIPE_CLK					62

#define GCC_PCIE_1_SLV_AXI_CLK					63

#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				64

#define GCC_PCIE_PHY_AUX_CLK					65

#define GCC_PCIE_PHY_REFGEN_CLK					66

#define GCC_PCIE_PHY_REFGEN_CLK_SRC				67

#define GCC_PDM2_CLK						68

#define GCC_PDM2_CLK_SRC					69

#define GCC_PDM_AHB_CLK						70

#define GCC_PDM_XO4_CLK						71

#define GCC_PRNG_AHB_CLK					72

#define GCC_QMIP_CAMERA_AHB_CLK					73

#define GCC_QMIP_DISP_AHB_CLK					74

#define GCC_QMIP_VIDEO_AHB_CLK					75

#define GCC_QUPV3_WRAP0_S0_CLK					76

#define GCC_QUPV3_WRAP0_S0_CLK_SRC				77

#define GCC_QUPV3_WRAP0_S1_CLK					78

#define GCC_QUPV3_WRAP0_S1_CLK_SRC				79

#define GCC_QUPV3_WRAP0_S2_CLK					80

#define GCC_QUPV3_WRAP0_S2_CLK_SRC				81

#define GCC_QUPV3_WRAP0_S3_CLK					82

#define GCC_QUPV3_WRAP0_S3_CLK_SRC				83

#define GCC_QUPV3_WRAP0_S4_CLK					84

#define GCC_QUPV3_WRAP0_S4_CLK_SRC				85

#define GCC_QUPV3_WRAP0_S5_CLK					86

#define GCC_QUPV3_WRAP0_S5_CLK_SRC				87

#define GCC_QUPV3_WRAP0_S6_CLK					88

#define GCC_QUPV3_WRAP0_S6_CLK_SRC				89

#define GCC_QUPV3_WRAP0_S7_CLK					90

#define GCC_QUPV3_WRAP0_S7_CLK_SRC				91

#define GCC_QUPV3_WRAP1_S0_CLK					92

#define GCC_QUPV3_WRAP1_S0_CLK_SRC				93

#define GCC_QUPV3_WRAP1_S1_CLK					94

#define GCC_QUPV3_WRAP1_S1_CLK_SRC				95

#define GCC_QUPV3_WRAP1_S2_CLK					96

#define GCC_QUPV3_WRAP1_S2_CLK_SRC				97

#define GCC_QUPV3_WRAP1_S3_CLK					98

#define GCC_QUPV3_WRAP1_S3_CLK_SRC				99

#define GCC_QUPV3_WRAP1_S4_CLK					100

#define GCC_QUPV3_WRAP1_S4_CLK_SRC				101

#define GCC_QUPV3_WRAP1_S5_CLK					102

#define GCC_QUPV3_WRAP1_S5_CLK_SRC				103

#define GCC_QUPV3_WRAP1_S6_CLK					104

#define GCC_QUPV3_WRAP1_S6_CLK_SRC				105

#define GCC_QUPV3_WRAP1_S7_CLK					106

#define GCC_QUPV3_WRAP1_S7_CLK_SRC				107

#define GCC_QUPV3_WRAP_0_M_AHB_CLK				108

#define GCC_QUPV3_WRAP_0_S_AHB_CLK				109

#define GCC_QUPV3_WRAP_1_M_AHB_CLK				110

#define GCC_QUPV3_WRAP_1_S_AHB_CLK				111

#define GCC_SDCC2_AHB_CLK					112

#define GCC_SDCC2_APPS_CLK					113

#define GCC_SDCC2_APPS_CLK_SRC					114

#define GCC_SDCC4_AHB_CLK					115

#define GCC_SDCC4_APPS_CLK					116

#define GCC_SDCC4_APPS_CLK_SRC					117

#define GCC_SYS_NOC_CPUSS_AHB_CLK				118

#define GCC_TSIF_AHB_CLK					119

#define GCC_TSIF_INACTIVITY_TIMERS_CLK				120

#define GCC_TSIF_REF_CLK					121

#define GCC_TSIF_REF_CLK_SRC					122

#define GCC_UFS_CARD_AHB_CLK					123

#define GCC_UFS_CARD_AXI_CLK					124

#define GCC_UFS_CARD_AXI_CLK_SRC				125

#define GCC_UFS_CARD_CLKREF_CLK					126

#define GCC_UFS_CARD_ICE_CORE_CLK				127

#define GCC_UFS_CARD_ICE_CORE_CLK_SRC				128

#define GCC_UFS_CARD_PHY_AUX_CLK				129

#define GCC_UFS_CARD_PHY_AUX_CLK_SRC				130

#define GCC_UFS_CARD_RX_SYMBOL_0_CLK				131

#define GCC_UFS_CARD_RX_SYMBOL_1_CLK				132

#define GCC_UFS_CARD_TX_SYMBOL_0_CLK				133

#define GCC_UFS_CARD_UNIPRO_CORE_CLK				134

#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			135

#define GCC_UFS_MEM_CLKREF_CLK					136

#define GCC_UFS_PHY_AHB_CLK					137

#define GCC_UFS_PHY_AXI_CLK					138

#define GCC_UFS_PHY_AXI_CLK_SRC					139

#define GCC_UFS_PHY_ICE_CORE_CLK				140

#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				141

#define GCC_UFS_PHY_PHY_AUX_CLK					142

#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				143

#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				144

#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				145

#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				146

#define GCC_UFS_PHY_UNIPRO_CORE_CLK				147

#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				148

#define GCC_USB30_PRIM_MASTER_CLK				149

#define GCC_USB30_PRIM_MASTER_CLK_SRC				150

#define GCC_USB30_PRIM_MOCK_UTMI_CLK				151

#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			152

#define GCC_USB30_PRIM_SLEEP_CLK				153

#define GCC_USB30_SEC_MASTER_CLK				154

#define GCC_USB30_SEC_MASTER_CLK_SRC				155

#define GCC_USB30_SEC_MOCK_UTMI_CLK				156

#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				157

#define GCC_USB30_SEC_SLEEP_CLK					158

#define GCC_USB3_PRIM_CLKREF_CLK				159

#define GCC_USB3_PRIM_PHY_AUX_CLK				160

#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				161

#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				162

#define GCC_USB3_PRIM_PHY_PIPE_CLK				163

#define GCC_USB3_SEC_CLKREF_CLK					164

#define GCC_USB3_SEC_PHY_AUX_CLK				165

#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				166

#define GCC_USB3_SEC_PHY_COM_AUX_CLK				167

#define GCC_USB3_SEC_PHY_PIPE_CLK				168

#define GCC_USB_PHY_CFG_AHB2PHY_CLK				169

#define GCC_VIDEO_AHB_CLK					170

#define GCC_VIDEO_AXI_CLK					171

#define GCC_VIDEO_XO_CLK					172

#define GPLL0							173

#define GPLL0_OUT_EVEN						174

#define GPLL0_OUT_MAIN						175

#define GCC_UFS_CARD_AXI_HW_CTL_CLK				176

#define GCC_UFS_PHY_AXI_HW_CTL_CLK				177

#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK			178

#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK			179

#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK			180

#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK				181

#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK			182

#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK			183

#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK				184

#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK				185

#define GCC_GPU_IREF_CLK					186

#define GCC_SDCC1_AHB_CLK					187

#define GCC_SDCC1_APPS_CLK					188

#define GCC_SDCC1_ICE_CORE_CLK					189

#define GCC_SDCC1_APPS_CLK_SRC					190

#define GCC_SDCC1_ICE_CORE_CLK_SRC				191

#define GCC_APC_VS_CLK						192

#define GCC_GPU_VS_CLK						193

#define GCC_MSS_VS_CLK						194

#define GCC_VDDA_VS_CLK						195

#define GCC_VDDCX_VS_CLK					196

#define GCC_VDDMX_VS_CLK					197

#define GCC_VS_CTRL_AHB_CLK					198

#define GCC_VS_CTRL_CLK						199

#define GCC_VS_CTRL_CLK_SRC					200

#define GCC_VSENSOR_CLK_SRC					201

#define GPLL4							202

#define GPLL6							203



/* GCC reset clocks */

#define GCC_MMSS_BCR						0
@@ -243,10 +251,4 @@ 
#define GCC_PCIE_1_PHY_BCR					25

#define GCC_SDCC1_BCR						26



/* Dummy clocks for rate measurement */

#define MEASURE_ONLY_SNOC_CLK					0

#define MEASURE_ONLY_CNOC_CLK					1

#define MEASURE_ONLY_BIMC_CLK					2

#define MEASURE_ONLY_IPA_2X_CLK					3



#endif