Loading drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c +27 −0 Original line number Diff line number Diff line Loading @@ -28,6 +28,24 @@ #define WBID(wb_enc) ((wb_enc) ? wb_enc->wb_dev->wb_idx : -1) #define TO_S15D16(_x_) ((_x_) << 7) /** * sde_rgb2yuv_601l - rgb to yuv color space conversion matrix * */ static struct sde_csc_cfg sde_encoder_phys_wb_rgb2yuv_601l = { { TO_S15D16(0x0083), TO_S15D16(0x0102), TO_S15D16(0x0032), TO_S15D16(0x1fb5), TO_S15D16(0x1f6c), TO_S15D16(0x00e1), TO_S15D16(0x00e1), TO_S15D16(0x1f45), TO_S15D16(0x1fdc) }, { 0x00, 0x00, 0x00 }, { 0x0040, 0x0200, 0x0200 }, { 0x000, 0x3ff, 0x000, 0x3ff, 0x000, 0x3ff }, { 0x040, 0x3ac, 0x040, 0x3c0, 0x040, 0x3c0 }, }; /** * sde_encoder_phys_wb_is_master - report wb always as master encoder */ Loading Loading @@ -150,6 +168,15 @@ void sde_encoder_phys_setup_cdm(struct sde_encoder_phys *phys_enc, cdm_cfg->h_cdwn_type, cdm_cfg->v_cdwn_type); if (hw_cdm && hw_cdm->ops.setup_csc_data) { ret = hw_cdm->ops.setup_csc_data(hw_cdm, &sde_encoder_phys_wb_rgb2yuv_601l); if (ret < 0) { SDE_ERROR("failed to setup CSC %d\n", ret); return; } } if (hw_cdm && hw_cdm->ops.setup_cdwn) { ret = hw_cdm->ops.setup_cdwn(hw_cdm, cdm_cfg); if (ret < 0) { Loading drivers/gpu/drm/msm/sde/sde_hw_cdm.c +4 −42 Original line number Diff line number Diff line Loading @@ -76,50 +76,12 @@ static struct sde_cdm_cfg *_cdm_offset(enum sde_cdm cdm, return ERR_PTR(-EINVAL); } static void sde_hw_cdm_setup_csc_10bit(struct sde_hw_cdm *ctx, static int sde_hw_cdm_setup_csc_10bit(struct sde_hw_cdm *ctx, struct sde_csc_cfg *data) { struct sde_hw_blk_reg_map *c = &ctx->hw; u32 csc_reg_off = CDM_CSC_10_MATRIX_COEFF_0; u32 val; /* matrix coeff */ val = data->csc_mv[0] | (data->csc_mv[1] << 16); SDE_REG_WRITE(c, csc_reg_off, val); val = data->csc_mv[2] | (data->csc_mv[3] << 16); SDE_REG_WRITE(c, csc_reg_off + 0x4, val); val = data->csc_mv[4] | (data->csc_mv[5] << 16); SDE_REG_WRITE(c, csc_reg_off + 0x8, val); val = data->csc_mv[6] | (data->csc_mv[7] << 16); SDE_REG_WRITE(c, csc_reg_off + 0xc, val); val = data->csc_mv[8]; SDE_REG_WRITE(c, csc_reg_off + 0x10, val); /* Pre clamp */ val = (data->csc_pre_lv[0] << 16) | data->csc_pre_lv[1]; SDE_REG_WRITE(c, csc_reg_off + 0x14, val); val = (data->csc_pre_lv[2] << 16) | data->csc_pre_lv[3]; SDE_REG_WRITE(c, csc_reg_off + 0x18, val); val = (data->csc_pre_lv[4] << 16) | data->csc_pre_lv[5]; SDE_REG_WRITE(c, csc_reg_off + 0x1c, val); /* Post clamp */ val = (data->csc_post_lv[0] << 16) | data->csc_post_lv[1]; SDE_REG_WRITE(c, csc_reg_off + 0x20, val); val = (data->csc_post_lv[2] << 16) | data->csc_post_lv[3]; SDE_REG_WRITE(c, csc_reg_off + 0x24, val); val = (data->csc_post_lv[4] << 16) | data->csc_post_lv[5]; SDE_REG_WRITE(c, csc_reg_off + 0x28, val); /* Pre-Bias */ SDE_REG_WRITE(c, csc_reg_off + 0x2c, data->csc_pre_bv[0]); SDE_REG_WRITE(c, csc_reg_off + 0x30, data->csc_pre_bv[1]); SDE_REG_WRITE(c, csc_reg_off + 0x34, data->csc_pre_bv[2]); /* Post-Bias */ SDE_REG_WRITE(c, csc_reg_off + 0x38, data->csc_post_bv[0]); SDE_REG_WRITE(c, csc_reg_off + 0x3c, data->csc_post_bv[1]); SDE_REG_WRITE(c, csc_reg_off + 0x40, data->csc_post_bv[2]); sde_hw_csc_setup(&ctx->hw, CDM_CSC_10_MATRIX_COEFF_0, data, true); return 0; } static int sde_hw_cdm_setup_cdwn(struct sde_hw_cdm *ctx, Loading drivers/gpu/drm/msm/sde/sde_hw_cdm.h +3 −2 Original line number Diff line number Diff line /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. /* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -65,8 +65,9 @@ struct sde_hw_cdm_ops { * to program a different matrix than default matrix. * @cdm: Pointer to the chroma down context structure * @data Pointer to CSC configuration data * return: 0 if success; error code otherwise */ void (*setup_csc_data)(struct sde_hw_cdm *cdm, int (*setup_csc_data)(struct sde_hw_cdm *cdm, struct sde_csc_cfg *data); /** Loading Loading
drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c +27 −0 Original line number Diff line number Diff line Loading @@ -28,6 +28,24 @@ #define WBID(wb_enc) ((wb_enc) ? wb_enc->wb_dev->wb_idx : -1) #define TO_S15D16(_x_) ((_x_) << 7) /** * sde_rgb2yuv_601l - rgb to yuv color space conversion matrix * */ static struct sde_csc_cfg sde_encoder_phys_wb_rgb2yuv_601l = { { TO_S15D16(0x0083), TO_S15D16(0x0102), TO_S15D16(0x0032), TO_S15D16(0x1fb5), TO_S15D16(0x1f6c), TO_S15D16(0x00e1), TO_S15D16(0x00e1), TO_S15D16(0x1f45), TO_S15D16(0x1fdc) }, { 0x00, 0x00, 0x00 }, { 0x0040, 0x0200, 0x0200 }, { 0x000, 0x3ff, 0x000, 0x3ff, 0x000, 0x3ff }, { 0x040, 0x3ac, 0x040, 0x3c0, 0x040, 0x3c0 }, }; /** * sde_encoder_phys_wb_is_master - report wb always as master encoder */ Loading Loading @@ -150,6 +168,15 @@ void sde_encoder_phys_setup_cdm(struct sde_encoder_phys *phys_enc, cdm_cfg->h_cdwn_type, cdm_cfg->v_cdwn_type); if (hw_cdm && hw_cdm->ops.setup_csc_data) { ret = hw_cdm->ops.setup_csc_data(hw_cdm, &sde_encoder_phys_wb_rgb2yuv_601l); if (ret < 0) { SDE_ERROR("failed to setup CSC %d\n", ret); return; } } if (hw_cdm && hw_cdm->ops.setup_cdwn) { ret = hw_cdm->ops.setup_cdwn(hw_cdm, cdm_cfg); if (ret < 0) { Loading
drivers/gpu/drm/msm/sde/sde_hw_cdm.c +4 −42 Original line number Diff line number Diff line Loading @@ -76,50 +76,12 @@ static struct sde_cdm_cfg *_cdm_offset(enum sde_cdm cdm, return ERR_PTR(-EINVAL); } static void sde_hw_cdm_setup_csc_10bit(struct sde_hw_cdm *ctx, static int sde_hw_cdm_setup_csc_10bit(struct sde_hw_cdm *ctx, struct sde_csc_cfg *data) { struct sde_hw_blk_reg_map *c = &ctx->hw; u32 csc_reg_off = CDM_CSC_10_MATRIX_COEFF_0; u32 val; /* matrix coeff */ val = data->csc_mv[0] | (data->csc_mv[1] << 16); SDE_REG_WRITE(c, csc_reg_off, val); val = data->csc_mv[2] | (data->csc_mv[3] << 16); SDE_REG_WRITE(c, csc_reg_off + 0x4, val); val = data->csc_mv[4] | (data->csc_mv[5] << 16); SDE_REG_WRITE(c, csc_reg_off + 0x8, val); val = data->csc_mv[6] | (data->csc_mv[7] << 16); SDE_REG_WRITE(c, csc_reg_off + 0xc, val); val = data->csc_mv[8]; SDE_REG_WRITE(c, csc_reg_off + 0x10, val); /* Pre clamp */ val = (data->csc_pre_lv[0] << 16) | data->csc_pre_lv[1]; SDE_REG_WRITE(c, csc_reg_off + 0x14, val); val = (data->csc_pre_lv[2] << 16) | data->csc_pre_lv[3]; SDE_REG_WRITE(c, csc_reg_off + 0x18, val); val = (data->csc_pre_lv[4] << 16) | data->csc_pre_lv[5]; SDE_REG_WRITE(c, csc_reg_off + 0x1c, val); /* Post clamp */ val = (data->csc_post_lv[0] << 16) | data->csc_post_lv[1]; SDE_REG_WRITE(c, csc_reg_off + 0x20, val); val = (data->csc_post_lv[2] << 16) | data->csc_post_lv[3]; SDE_REG_WRITE(c, csc_reg_off + 0x24, val); val = (data->csc_post_lv[4] << 16) | data->csc_post_lv[5]; SDE_REG_WRITE(c, csc_reg_off + 0x28, val); /* Pre-Bias */ SDE_REG_WRITE(c, csc_reg_off + 0x2c, data->csc_pre_bv[0]); SDE_REG_WRITE(c, csc_reg_off + 0x30, data->csc_pre_bv[1]); SDE_REG_WRITE(c, csc_reg_off + 0x34, data->csc_pre_bv[2]); /* Post-Bias */ SDE_REG_WRITE(c, csc_reg_off + 0x38, data->csc_post_bv[0]); SDE_REG_WRITE(c, csc_reg_off + 0x3c, data->csc_post_bv[1]); SDE_REG_WRITE(c, csc_reg_off + 0x40, data->csc_post_bv[2]); sde_hw_csc_setup(&ctx->hw, CDM_CSC_10_MATRIX_COEFF_0, data, true); return 0; } static int sde_hw_cdm_setup_cdwn(struct sde_hw_cdm *ctx, Loading
drivers/gpu/drm/msm/sde/sde_hw_cdm.h +3 −2 Original line number Diff line number Diff line /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. /* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and Loading Loading @@ -65,8 +65,9 @@ struct sde_hw_cdm_ops { * to program a different matrix than default matrix. * @cdm: Pointer to the chroma down context structure * @data Pointer to CSC configuration data * return: 0 if success; error code otherwise */ void (*setup_csc_data)(struct sde_hw_cdm *cdm, int (*setup_csc_data)(struct sde_hw_cdm *cdm, struct sde_csc_cfg *data); /** Loading