Loading arch/arm/include/asm/assembler.h +42 −0 Original line number Diff line number Diff line Loading @@ -23,6 +23,7 @@ #include <asm/ptrace.h> #include <asm/domain.h> #include <asm/opcodes-virt.h> #include <asm/asm-offsets.h> #define IOMEM(x) (x) Loading Loading @@ -174,6 +175,47 @@ restore_irqs_notrace \oldcpsr .endm /* * Get current thread_info. */ .macro get_thread_info, rd ARM( mov \rd, sp, lsr #13 ) THUMB( mov \rd, sp ) THUMB( lsr \rd, \rd, #13 ) mov \rd, \rd, lsl #13 .endm /* * Increment/decrement the preempt count. */ #ifdef CONFIG_PREEMPT_COUNT .macro inc_preempt_count, ti, tmp ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count add \tmp, \tmp, #1 @ increment it str \tmp, [\ti, #TI_PREEMPT] .endm .macro dec_preempt_count, ti, tmp ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count sub \tmp, \tmp, #1 @ decrement it str \tmp, [\ti, #TI_PREEMPT] .endm .macro dec_preempt_count_ti, ti, tmp get_thread_info \ti dec_preempt_count \ti, \tmp .endm #else .macro inc_preempt_count, ti, tmp .endm .macro dec_preempt_count, ti, tmp .endm .macro dec_preempt_count_ti, ti, tmp .endm #endif #define USER(x...) \ 9999: x; \ .pushsection __ex_table,"a"; \ Loading arch/arm/include/asm/cputype.h +19 −0 Original line number Diff line number Diff line Loading @@ -221,4 +221,23 @@ static inline int cpu_is_xsc3(void) #define cpu_is_xscale() 1 #endif /* * Marvell's PJ4 core is based on V7 version. It has some modification * for coprocessor setting. For this reason, we need a way to distinguish * it. */ #ifndef CONFIG_CPU_PJ4 #define cpu_is_pj4() 0 #else static inline int cpu_is_pj4(void) { unsigned int id; id = read_cpuid_id(); if ((id & 0xfffffff0) == 0x562f5840) return 1; return 0; } #endif #endif arch/arm/kernel/crash_dump.c +1 −1 Original line number Diff line number Diff line Loading @@ -39,7 +39,7 @@ ssize_t copy_oldmem_page(unsigned long pfn, char *buf, if (!csize) return 0; vaddr = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE); vaddr = ioremap(__pfn_to_phys(pfn), PAGE_SIZE); if (!vaddr) return -ENOMEM; Loading arch/arm/kernel/entry-header.S +0 −11 Original line number Diff line number Diff line Loading @@ -236,11 +236,6 @@ movs pc, lr @ return & move spsr_svc into cpsr .endm .macro get_thread_info, rd mov \rd, sp, lsr #13 mov \rd, \rd, lsl #13 .endm @ @ 32-bit wide "mov pc, reg" @ Loading Loading @@ -306,12 +301,6 @@ .endm #endif /* ifdef CONFIG_CPU_V7M / else */ .macro get_thread_info, rd mov \rd, sp lsr \rd, \rd, #13 mov \rd, \rd, lsl #13 .endm @ @ 32-bit wide "mov pc, reg" @ Loading arch/arm/kernel/pj4-cp0.c +4 −0 Original line number Diff line number Diff line Loading @@ -17,6 +17,7 @@ #include <linux/init.h> #include <linux/io.h> #include <asm/thread_notify.h> #include <asm/cputype.h> static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t) { Loading Loading @@ -80,6 +81,9 @@ static int __init pj4_cp0_init(void) { u32 cp_access; if (!cpu_is_pj4()) return 0; cp_access = pj4_cp_access_read() & ~0xf; pj4_cp_access_write(cp_access); Loading Loading
arch/arm/include/asm/assembler.h +42 −0 Original line number Diff line number Diff line Loading @@ -23,6 +23,7 @@ #include <asm/ptrace.h> #include <asm/domain.h> #include <asm/opcodes-virt.h> #include <asm/asm-offsets.h> #define IOMEM(x) (x) Loading Loading @@ -174,6 +175,47 @@ restore_irqs_notrace \oldcpsr .endm /* * Get current thread_info. */ .macro get_thread_info, rd ARM( mov \rd, sp, lsr #13 ) THUMB( mov \rd, sp ) THUMB( lsr \rd, \rd, #13 ) mov \rd, \rd, lsl #13 .endm /* * Increment/decrement the preempt count. */ #ifdef CONFIG_PREEMPT_COUNT .macro inc_preempt_count, ti, tmp ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count add \tmp, \tmp, #1 @ increment it str \tmp, [\ti, #TI_PREEMPT] .endm .macro dec_preempt_count, ti, tmp ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count sub \tmp, \tmp, #1 @ decrement it str \tmp, [\ti, #TI_PREEMPT] .endm .macro dec_preempt_count_ti, ti, tmp get_thread_info \ti dec_preempt_count \ti, \tmp .endm #else .macro inc_preempt_count, ti, tmp .endm .macro dec_preempt_count, ti, tmp .endm .macro dec_preempt_count_ti, ti, tmp .endm #endif #define USER(x...) \ 9999: x; \ .pushsection __ex_table,"a"; \ Loading
arch/arm/include/asm/cputype.h +19 −0 Original line number Diff line number Diff line Loading @@ -221,4 +221,23 @@ static inline int cpu_is_xsc3(void) #define cpu_is_xscale() 1 #endif /* * Marvell's PJ4 core is based on V7 version. It has some modification * for coprocessor setting. For this reason, we need a way to distinguish * it. */ #ifndef CONFIG_CPU_PJ4 #define cpu_is_pj4() 0 #else static inline int cpu_is_pj4(void) { unsigned int id; id = read_cpuid_id(); if ((id & 0xfffffff0) == 0x562f5840) return 1; return 0; } #endif #endif
arch/arm/kernel/crash_dump.c +1 −1 Original line number Diff line number Diff line Loading @@ -39,7 +39,7 @@ ssize_t copy_oldmem_page(unsigned long pfn, char *buf, if (!csize) return 0; vaddr = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE); vaddr = ioremap(__pfn_to_phys(pfn), PAGE_SIZE); if (!vaddr) return -ENOMEM; Loading
arch/arm/kernel/entry-header.S +0 −11 Original line number Diff line number Diff line Loading @@ -236,11 +236,6 @@ movs pc, lr @ return & move spsr_svc into cpsr .endm .macro get_thread_info, rd mov \rd, sp, lsr #13 mov \rd, \rd, lsl #13 .endm @ @ 32-bit wide "mov pc, reg" @ Loading Loading @@ -306,12 +301,6 @@ .endm #endif /* ifdef CONFIG_CPU_V7M / else */ .macro get_thread_info, rd mov \rd, sp lsr \rd, \rd, #13 mov \rd, \rd, lsl #13 .endm @ @ 32-bit wide "mov pc, reg" @ Loading
arch/arm/kernel/pj4-cp0.c +4 −0 Original line number Diff line number Diff line Loading @@ -17,6 +17,7 @@ #include <linux/init.h> #include <linux/io.h> #include <asm/thread_notify.h> #include <asm/cputype.h> static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t) { Loading Loading @@ -80,6 +81,9 @@ static int __init pj4_cp0_init(void) { u32 cp_access; if (!cpu_is_pj4()) return 0; cp_access = pj4_cp_access_read() & ~0xf; pj4_cp_access_write(cp_access); Loading