Merge "msm: kgsl: Add secure preemption support for A6XX" (5323339b) · Commits · e / devices / android_kernel_fairphone_FP3

drivers/gpu/msm/adreno_a6xx.c

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -907,7 +907,8 @@ static int _preemption_init(struct adreno_device *adreno_dev,
	rb->preemption_desc.gpuaddr);		rb->preemption_desc.gpuaddr);

	*cmds++ = 2;		*cmds++ = 2;
	cmds += cp_gpuaddr(adreno_dev, cmds, 0);		cmds += cp_gpuaddr(adreno_dev, cmds,
			rb->secure_preemption_desc.gpuaddr);

	/* Turn CP protection ON */		/* Turn CP protection ON */
	*cmds++ = cp_type7_packet(CP_SET_PROTECTED_MODE, 1);		*cmds++ = cp_type7_packet(CP_SET_PROTECTED_MODE, 1);

drivers/gpu/msm/adreno_a6xx_preempt.c

+31 −2

Original line number	Original line	Diff line number	Diff line
	@@ -332,6 +332,16 @@ void a6xx_preemption_trigger(struct adreno_device *adreno_dev)
	upper_32_bits(next->preemption_desc.gpuaddr),		upper_32_bits(next->preemption_desc.gpuaddr),
	FENCE_STATUS_WRITEDROPPED1_MASK);		FENCE_STATUS_WRITEDROPPED1_MASK);

			adreno_gmu_fenced_write(adreno_dev,
			ADRENO_REG_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO,
			lower_32_bits(next->secure_preemption_desc.gpuaddr),
			FENCE_STATUS_WRITEDROPPED1_MASK);

			adreno_gmu_fenced_write(adreno_dev,
			ADRENO_REG_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI,
			upper_32_bits(next->secure_preemption_desc.gpuaddr),
			FENCE_STATUS_WRITEDROPPED1_MASK);

	adreno_gmu_fenced_write(adreno_dev,		adreno_gmu_fenced_write(adreno_dev,
	ADRENO_REG_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO,		ADRENO_REG_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO,
	lower_32_bits(gpuaddr),		lower_32_bits(gpuaddr),
	@@ -455,7 +465,8 @@ unsigned int a6xx_preemption_pre_ibsubmit(
	cmds += cp_gpuaddr(adreno_dev, cmds, rb->preemption_desc.gpuaddr);		cmds += cp_gpuaddr(adreno_dev, cmds, rb->preemption_desc.gpuaddr);

	*cmds++ = SET_PSEUDO_REGISTER_SAVE_REGISTER_PRIV_SECURE_SAVE_ADDR;		*cmds++ = SET_PSEUDO_REGISTER_SAVE_REGISTER_PRIV_SECURE_SAVE_ADDR;
	cmds += cp_gpuaddr(adreno_dev, cmds, 0);		cmds += cp_gpuaddr(adreno_dev, cmds,
			rb->secure_preemption_desc.gpuaddr);

	if (context) {		if (context) {

	@@ -574,6 +585,17 @@ static int a6xx_preemption_ringbuffer_init(struct adreno_device *adreno_dev,
	if (ret)		if (ret)
	return ret;		return ret;

			ret = kgsl_allocate_user(device, &rb->secure_preemption_desc,
			A6XX_CP_CTXRECORD_SIZE_IN_BYTES,
			KGSL_MEMFLAGS_SECURE \| KGSL_MEMDESC_PRIVILEGED);
			if (ret)
			return ret;

			ret = kgsl_iommu_map_global_secure_pt_entry(device,
			&rb->secure_preemption_desc);
			if (ret)
			return ret;

	ret = kgsl_allocate_global(device, &rb->perfcounter_save_restore_desc,		ret = kgsl_allocate_global(device, &rb->perfcounter_save_restore_desc,
	A6XX_CP_PERFCOUNTER_SAVE_RESTORE_SIZE, 0,		A6XX_CP_PERFCOUNTER_SAVE_RESTORE_SIZE, 0,
	KGSL_MEMDESC_PRIVILEGED, "perfcounter_save_restore_desc");		KGSL_MEMDESC_PRIVILEGED, "perfcounter_save_restore_desc");
	@@ -647,6 +669,9 @@ static void a6xx_preemption_close(struct kgsl_device *device)
	FOR_EACH_RINGBUFFER(adreno_dev, rb, i) {		FOR_EACH_RINGBUFFER(adreno_dev, rb, i) {
	kgsl_free_global(device, &rb->preemption_desc);		kgsl_free_global(device, &rb->preemption_desc);
	kgsl_free_global(device, &rb->perfcounter_save_restore_desc);		kgsl_free_global(device, &rb->perfcounter_save_restore_desc);
			kgsl_iommu_unmap_global_secure_pt_entry(device,
			&rb->secure_preemption_desc);
			kgsl_sharedmem_free(&rb->secure_preemption_desc);
	}		}
	}		}

	@@ -714,16 +739,20 @@ int a6xx_preemption_context_init(struct kgsl_context *context)
	{		{
	struct kgsl_device *device = context->device;		struct kgsl_device *device = context->device;
	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);		struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
			uint64_t flags = 0;

	if (!adreno_is_preemption_setup_enabled(adreno_dev))		if (!adreno_is_preemption_setup_enabled(adreno_dev))
	return 0;		return 0;

			if (context->flags & KGSL_CONTEXT_SECURE)
			flags \|= KGSL_MEMFLAGS_SECURE;

	/*		/*
	* gpumem_alloc_entry takes an extra refcount. Put it only when		* gpumem_alloc_entry takes an extra refcount. Put it only when
	* destroying the context to keep the context record valid		* destroying the context to keep the context record valid
	*/		*/
	context->user_ctxt_record = gpumem_alloc_entry(context->dev_priv,		context->user_ctxt_record = gpumem_alloc_entry(context->dev_priv,
	A6XX_CP_CTXRECORD_USER_RESTORE_SIZE, 0);		A6XX_CP_CTXRECORD_USER_RESTORE_SIZE, flags);
	if (IS_ERR(context->user_ctxt_record)) {		if (IS_ERR(context->user_ctxt_record)) {
	int ret = PTR_ERR(context->user_ctxt_record);		int ret = PTR_ERR(context->user_ctxt_record);

drivers/gpu/msm/adreno_ringbuffer.h

+3 −0

Original line number	Original line	Diff line number	Diff line
	@@ -92,6 +92,8 @@ struct adreno_ringbuffer_pagetable_info {
	* @drawctxt_active: The last pagetable that this ringbuffer is set to		* @drawctxt_active: The last pagetable that this ringbuffer is set to
	* @preemption_desc: The memory descriptor containing		* @preemption_desc: The memory descriptor containing
	* preemption info written/read by CP		* preemption info written/read by CP
			* @secure_preemption_desc: The memory descriptor containing
			* preemption info written/read by CP for secure contexts
	* @perfcounter_save_restore_desc: Used by CP to save/restore the perfcounter		* @perfcounter_save_restore_desc: Used by CP to save/restore the perfcounter
	* values across preemption		* values across preemption
	* @pagetable_desc: Memory to hold information about the pagetables being used		* @pagetable_desc: Memory to hold information about the pagetables being used
	@@ -120,6 +122,7 @@ struct adreno_ringbuffer {
	struct kgsl_event_group events;		struct kgsl_event_group events;
	struct adreno_context *drawctxt_active;		struct adreno_context *drawctxt_active;
	struct kgsl_memdesc preemption_desc;		struct kgsl_memdesc preemption_desc;
			struct kgsl_memdesc secure_preemption_desc;
	struct kgsl_memdesc perfcounter_save_restore_desc;		struct kgsl_memdesc perfcounter_save_restore_desc;
	struct kgsl_memdesc pagetable_desc;		struct kgsl_memdesc pagetable_desc;
	struct adreno_dispatcher_drawqueue dispatch_q;		struct adreno_dispatcher_drawqueue dispatch_q;