Loading drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_10_0_0_hwreg.h +4 −0 Original line number Diff line number Diff line Loading @@ -72,6 +72,10 @@ static struct csiphy_reg_snps_parms_t csiphy_v10_0_0_snps = { {0x12c, 0x0}, /* mipi_csiphy_rx_lane_0_7_00 */ {0x220, 0x0}, /* mipi_csiphy_rx_lane_1_7_00 */ {0xCC, 0x0}, /* mipi_csiphy_rx_clk_lane_7_00 */ {0x1F8, 0x20}, /* mipi_csiphy_rx_lane0_ddl_2_00 */ {0x1FC, 0x10}, /* mipi_csiphy_rx_lane0_ddl_3_00 */ {0x22C, 0x80}, /* mipi_csiphy_rx_lane_1_10_00 */ {0x230, 0x10}, /* mipi_csiphy_rx_lane_1_11_00 */ }; static struct snps_freq_value snps_v100_freq_values[] = { Loading drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c +21 −0 Original line number Diff line number Diff line Loading @@ -282,6 +282,27 @@ static int msm_csiphy_snps_2_lane_config( csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg. mipi_csiphy_rx_cb_2_00.addr + offset); if (local_data_rate <= 1500) { msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg. mipi_csiphy_rx_lane0_ddl_2_00.data, csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg. mipi_csiphy_rx_lane0_ddl_2_00.addr + offset); msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg. mipi_csiphy_rx_lane0_ddl_3_00.data, csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg. mipi_csiphy_rx_lane0_ddl_3_00.addr + offset); msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg. mipi_csiphy_rx_lane_1_10_00.data, csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg. mipi_csiphy_rx_lane_1_10_00.addr + offset); msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg. mipi_csiphy_rx_lane_1_11_00.data, csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg. mipi_csiphy_rx_lane_1_11_00.addr + offset); } return 0; } Loading drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h +4 −0 Original line number Diff line number Diff line Loading @@ -99,6 +99,10 @@ struct csiphy_reg_snps_parms_t { struct csiphy_reg_t mipi_csiphy_rx_lane_0_7_00; struct csiphy_reg_t mipi_csiphy_rx_lane_1_7_00; struct csiphy_reg_t mipi_csiphy_rx_clk_lane_7_00; struct csiphy_reg_t mipi_csiphy_rx_lane0_ddl_2_00; struct csiphy_reg_t mipi_csiphy_rx_lane0_ddl_3_00; struct csiphy_reg_t mipi_csiphy_rx_lane_1_10_00; struct csiphy_reg_t mipi_csiphy_rx_lane_1_11_00; }; struct csiphy_reg_3ph_parms_t { Loading Loading
drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_10_0_0_hwreg.h +4 −0 Original line number Diff line number Diff line Loading @@ -72,6 +72,10 @@ static struct csiphy_reg_snps_parms_t csiphy_v10_0_0_snps = { {0x12c, 0x0}, /* mipi_csiphy_rx_lane_0_7_00 */ {0x220, 0x0}, /* mipi_csiphy_rx_lane_1_7_00 */ {0xCC, 0x0}, /* mipi_csiphy_rx_clk_lane_7_00 */ {0x1F8, 0x20}, /* mipi_csiphy_rx_lane0_ddl_2_00 */ {0x1FC, 0x10}, /* mipi_csiphy_rx_lane0_ddl_3_00 */ {0x22C, 0x80}, /* mipi_csiphy_rx_lane_1_10_00 */ {0x230, 0x10}, /* mipi_csiphy_rx_lane_1_11_00 */ }; static struct snps_freq_value snps_v100_freq_values[] = { Loading
drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c +21 −0 Original line number Diff line number Diff line Loading @@ -282,6 +282,27 @@ static int msm_csiphy_snps_2_lane_config( csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg. mipi_csiphy_rx_cb_2_00.addr + offset); if (local_data_rate <= 1500) { msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg. mipi_csiphy_rx_lane0_ddl_2_00.data, csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg. mipi_csiphy_rx_lane0_ddl_2_00.addr + offset); msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg. mipi_csiphy_rx_lane0_ddl_3_00.data, csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg. mipi_csiphy_rx_lane0_ddl_3_00.addr + offset); msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg. mipi_csiphy_rx_lane_1_10_00.data, csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg. mipi_csiphy_rx_lane_1_10_00.addr + offset); msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg. mipi_csiphy_rx_lane_1_11_00.data, csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg. mipi_csiphy_rx_lane_1_11_00.addr + offset); } return 0; } Loading
drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h +4 −0 Original line number Diff line number Diff line Loading @@ -99,6 +99,10 @@ struct csiphy_reg_snps_parms_t { struct csiphy_reg_t mipi_csiphy_rx_lane_0_7_00; struct csiphy_reg_t mipi_csiphy_rx_lane_1_7_00; struct csiphy_reg_t mipi_csiphy_rx_clk_lane_7_00; struct csiphy_reg_t mipi_csiphy_rx_lane0_ddl_2_00; struct csiphy_reg_t mipi_csiphy_rx_lane0_ddl_3_00; struct csiphy_reg_t mipi_csiphy_rx_lane_1_10_00; struct csiphy_reg_t mipi_csiphy_rx_lane_1_11_00; }; struct csiphy_reg_3ph_parms_t { Loading