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Commit 52e329eb authored by Kukjin Kim's avatar Kukjin Kim
Browse files

ARM: SAMSUNG: Consolidate plat/pll.h 



Removed
- arch/arm/plat-s3c24xx/include/plat/pll.h
- arch/arm/mach-s3c64xx/include/mach/pll.h
- arch/arm/plat-s5p/include/plat/pll.h
- arch/arm/plat-samsung/include/plat/pll6553x.h

And created
- arch/arm/plat-samsung/include/plat/pll.h

Cc: Ben Dooks <ben-linux@fluff.org>
[kgene.kim@samsung.com: changed title]
[kgene.kim@samsung.com: fixed conflicts in plat-s5p/include/pll.h]
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent c0468b02

arch/arm/mach-s3c2410/mach-h1940.c

+3 −3
Original line number Diff line number Diff line
@@ -696,9 +696,9 @@ static void __init h1940_init(void) 
			      S3C2410_MISCCR_USBSUSPND0 |

			      S3C2410_MISCCR_USBSUSPND1, 0x0);



	tmp =   (0x78 << S3C24XX_PLLCON_MDIVSHIFT)

	      | (0x02 << S3C24XX_PLLCON_PDIVSHIFT)

	      | (0x03 << S3C24XX_PLLCON_SDIVSHIFT);

	tmp =   (0x78 << S3C24XX_PLL_MDIV_SHIFT)

	      | (0x02 << S3C24XX_PLL_PDIV_SHIFT)

	      | (0x03 << S3C24XX_PLL_SDIV_SHIFT);

	writel(tmp, S3C2410_UPLLCON);



	gpio_request(S3C2410_GPC(0), "LCD power");

arch/arm/mach-s3c2416/clock.c

+0 −1
Original line number Diff line number Diff line
@@ -21,7 +21,6 @@ 
#include <plat/cpu.h>



#include <plat/cpu-freq.h>

#include <plat/pll6553x.h>

#include <plat/pll.h>



#include <asm/mach/map.h>

arch/arm/mach-s3c64xx/clock.c

+3 −2
Original line number Diff line number Diff line
@@ -25,13 +25,13 @@ 


#include <mach/regs-sys.h>

#include <mach/regs-clock.h>

#include <mach/pll.h>



#include <plat/cpu.h>

#include <plat/devs.h>

#include <plat/cpu-freq.h>

#include <plat/clock.h>

#include <plat/clock-clksrc.h>

#include <plat/pll.h>



/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call

 * ext_xtal_mux for want of an actual name from the manual.
@@ -735,7 +735,8 @@ void __init_or_cpufreq s3c6400_setup_clocks(void) 
	/* For now assume the mux always selects the crystal */

	clk_ext_xtal_mux.parent = xtal_clk;



	epll = s3c6400_get_epll(xtal);

	epll = s3c_get_pll6553x(xtal, __raw_readl(S3C_EPLL_CON0),

				__raw_readl(S3C_EPLL_CON1));

	mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));

	apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));

arch/arm/mach-s3c64xx/include/mach/pll.h

deleted100644 → 0
+0 −45
Original line number Diff line number Diff line 
/* arch/arm/plat-s3c64xx/include/plat/pll.h

 *

 * Copyright 2008 Openmoko, Inc.

 * Copyright 2008 Simtec Electronics

 *	Ben Dooks <ben@simtec.co.uk>

 *	http://armlinux.simtec.co.uk/

 *

 * S3C64XX PLL code

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

*/



#define S3C6400_PLL_MDIV_MASK	((1 << (25-16+1)) - 1)

#define S3C6400_PLL_PDIV_MASK	((1 << (13-8+1)) - 1)

#define S3C6400_PLL_SDIV_MASK	((1 << (2-0+1)) - 1)

#define S3C6400_PLL_MDIV_SHIFT	(16)

#define S3C6400_PLL_PDIV_SHIFT	(8)

#define S3C6400_PLL_SDIV_SHIFT	(0)



#include <asm/div64.h>

#include <plat/pll6553x.h>



static inline unsigned long s3c6400_get_pll(unsigned long baseclk,

					    u32 pllcon)

{

	u32 mdiv, pdiv, sdiv;

	u64 fvco = baseclk;



	mdiv = (pllcon >> S3C6400_PLL_MDIV_SHIFT) & S3C6400_PLL_MDIV_MASK;

	pdiv = (pllcon >> S3C6400_PLL_PDIV_SHIFT) & S3C6400_PLL_PDIV_MASK;

	sdiv = (pllcon >> S3C6400_PLL_SDIV_SHIFT) & S3C6400_PLL_SDIV_MASK;



	fvco *= mdiv;

	do_div(fvco, (pdiv << sdiv));



	return (unsigned long)fvco;

}



static inline unsigned long s3c6400_get_epll(unsigned long baseclk)

{

	return s3c_get_pll6553x(baseclk, __raw_readl(S3C_EPLL_CON0),

				__raw_readl(S3C_EPLL_CON1));

}

arch/arm/plat-s3c24xx/include/plat/pll.h

deleted100644 → 0
+0 −62
Original line number Diff line number Diff line 
/* linux/arch/arm/plat-s3c24xx/include/plat/pll.h

 *

 * Copyright 2008 Simtec Electronics

 *      Ben Dooks <ben@simtec.co.uk>

 *      http://armlinux.simtec.co.uk/

 *

 * S3C24xx - common pll registers and code

 */



#define S3C24XX_PLLCON_MDIVSHIFT	12

#define S3C24XX_PLLCON_PDIVSHIFT	4

#define S3C24XX_PLLCON_SDIVSHIFT	0

#define S3C24XX_PLLCON_MDIVMASK		((1<<(1+(19-12)))-1)

#define S3C24XX_PLLCON_PDIVMASK		((1<<5)-1)

#define S3C24XX_PLLCON_SDIVMASK		3



#include <asm/div64.h>



static inline unsigned int

s3c24xx_get_pll(unsigned int pllval, unsigned int baseclk)

{

	unsigned int mdiv, pdiv, sdiv;

	uint64_t fvco;



	mdiv = pllval >> S3C24XX_PLLCON_MDIVSHIFT;

	pdiv = pllval >> S3C24XX_PLLCON_PDIVSHIFT;

	sdiv = pllval >> S3C24XX_PLLCON_SDIVSHIFT;



	mdiv &= S3C24XX_PLLCON_MDIVMASK;

	pdiv &= S3C24XX_PLLCON_PDIVMASK;

	sdiv &= S3C24XX_PLLCON_SDIVMASK;



	fvco = (uint64_t)baseclk * (mdiv + 8);

	do_div(fvco, (pdiv + 2) << sdiv);



	return (unsigned int)fvco;

}



#define S3C2416_PLL_M_SHIFT	(14)

#define S3C2416_PLL_P_SHIFT	(5)

#define S3C2416_PLL_S_MASK	(7)

#define S3C2416_PLL_M_MASK	((1 << 10) - 1)

#define S3C2416_PLL_P_MASK	(63)



static inline unsigned int

s3c2416_get_pll(unsigned int pllval, unsigned int baseclk)

{

	unsigned int m, p, s;

	uint64_t fvco;



	m = pllval >> S3C2416_PLL_M_SHIFT;

	p = pllval >> S3C2416_PLL_P_SHIFT;



	s = pllval & S3C2416_PLL_S_MASK;

	m &= S3C2416_PLL_M_MASK;

	p &= S3C2416_PLL_P_MASK;



	fvco = (uint64_t)baseclk * m;

	do_div(fvco, (p << s));



	return (unsigned int)fvco;

}