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Commit 52dffd7f authored by Poonam Aggrwal's avatar Poonam Aggrwal Committed by Kumar Gala
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powerpc/85xx: Added P1020RDB Platform support. 



P1020 is another member of Freescale QorIQ series of processors.
It is an e500 based dual core SOC.
Being a scaled down version of P2020 it has following differences from P2020:
- 533MHz - 800MHz core frequency.
- 256Kbyte L2 cache
- Ethernet controllers with classification capabilities(new controller).

From board perspective P1020RDB is same as P2020RDB.

Signed-off-by: default avatarPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 46d22934

arch/powerpc/boot/dts/p1020rdb.dts

0 → 100644
+477 −0
Original line number Original line Diff line number Diff line 
/*

 * P1020 RDB Device Tree Source

 *

 * Copyright 2009 Freescale Semiconductor Inc.

 *

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 */



/dts-v1/;

/ {

	model = "fsl,P1020";

	compatible = "fsl,P1020RDB";

	#address-cells = <2>;

	#size-cells = <2>;



	aliases {

		serial0 = &serial0;

		serial1 = &serial1;

		pci0 = &pci0;

		pci1 = &pci1;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;



		PowerPC,P1020@0 {

			device_type = "cpu";

			reg = <0x0>;

			next-level-cache = <&L2>;

		};



		PowerPC,P1020@1 {

			device_type = "cpu";

			reg = <0x1>;

			next-level-cache = <&L2>;

		};

	};



	memory {

		device_type = "memory";

	};



	localbus@ffe05000 {

		#address-cells = <2>;

		#size-cells = <1>;

		compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";

		reg = <0 0xffe05000 0 0x1000>;

		interrupts = <19 2>;

		interrupt-parent = <&mpic>;



		/* NOR, NAND Flashes and Vitesse 5 port L2 switch */

		ranges = <0x0 0x0 0x0 0xef000000 0x01000000

			  0x1 0x0 0x0 0xffa00000 0x00040000

			  0x2 0x0 0x0 0xffb00000 0x00020000>;



		nor@0,0 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "cfi-flash";

			reg = <0x0 0x0 0x1000000>;

			bank-width = <2>;

			device-width = <1>;



			partition@0 {

				/* This location must not be altered  */

				/* 256KB for Vitesse 7385 Switch firmware */

				reg = <0x0 0x00040000>;

				label = "NOR (RO) Vitesse-7385 Firmware";

				read-only;

			};



			partition@40000 {

				/* 256KB for DTB Image */

				reg = <0x00040000 0x00040000>;

				label = "NOR (RO) DTB Image";

				read-only;

			};



			partition@80000 {

				/* 3.5 MB for Linux Kernel Image */

				reg = <0x00080000 0x00380000>;

				label = "NOR (RO) Linux Kernel Image";

				read-only;

			};



			partition@400000 {

				/* 11MB for JFFS2 based Root file System */

				reg = <0x00400000 0x00b00000>;

				label = "NOR (RW) JFFS2 Root File System";

			};



			partition@f00000 {

				/* This location must not be altered  */

				/* 512KB for u-boot Bootloader Image */

				/* 512KB for u-boot Environment Variables */

				reg = <0x00f00000 0x00100000>;

				label = "NOR (RO) U-Boot Image";

				read-only;

			};

		};



		nand@1,0 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "fsl,p1020-fcm-nand",

				     "fsl,elbc-fcm-nand";

			reg = <0x1 0x0 0x40000>;



			partition@0 {

				/* This location must not be altered  */

				/* 1MB for u-boot Bootloader Image */

				reg = <0x0 0x00100000>;

				label = "NAND (RO) U-Boot Image";

				read-only;

			};



			partition@100000 {

				/* 1MB for DTB Image */

				reg = <0x00100000 0x00100000>;

				label = "NAND (RO) DTB Image";

				read-only;

			};



			partition@200000 {

				/* 4MB for Linux Kernel Image */

				reg = <0x00200000 0x00400000>;

				label = "NAND (RO) Linux Kernel Image";

				read-only;

			};



			partition@600000 {

				/* 4MB for Compressed Root file System Image */

				reg = <0x00600000 0x00400000>;

				label = "NAND (RO) Compressed RFS Image";

				read-only;

			};



			partition@a00000 {

				/* 7MB for JFFS2 based Root file System */

				reg = <0x00a00000 0x00700000>;

				label = "NAND (RW) JFFS2 Root File System";

			};



			partition@1100000 {

				/* 15MB for JFFS2 based Root file System */

				reg = <0x01100000 0x00f00000>;

				label = "NAND (RW) Writable User area";

			};

		};



		L2switch@2,0 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "vitesse-7385";

			reg = <0x2 0x0 0x20000>;

		};



	};



	soc@ffe00000 {

		#address-cells = <1>;

		#size-cells = <1>;

		device_type = "soc";

		compatible = "fsl,p1020-immr", "simple-bus";

		ranges = <0x0  0x0 0xffe00000 0x100000>;

		bus-frequency = <0>;		// Filled out by uboot.



		ecm-law@0 {

			compatible = "fsl,ecm-law";

			reg = <0x0 0x1000>;

			fsl,num-laws = <12>;

		};



		ecm@1000 {

			compatible = "fsl,p1020-ecm", "fsl,ecm";

			reg = <0x1000 0x1000>;

			interrupts = <16 2>;

			interrupt-parent = <&mpic>;

		};



		memory-controller@2000 {

			compatible = "fsl,p1020-memory-controller";

			reg = <0x2000 0x1000>;

			interrupt-parent = <&mpic>;

			interrupts = <16 2>;

		};



		i2c@3000 {

			#address-cells = <1>;

			#size-cells = <0>;

			cell-index = <0>;

			compatible = "fsl-i2c";

			reg = <0x3000 0x100>;

			interrupts = <43 2>;

			interrupt-parent = <&mpic>;

			dfsrr;

			rtc@68 {

				compatible = "dallas,ds1339";

				reg = <0x68>;

			};

		};



		i2c@3100 {

			#address-cells = <1>;

			#size-cells = <0>;

			cell-index = <1>;

			compatible = "fsl-i2c";

			reg = <0x3100 0x100>;

			interrupts = <43 2>;

			interrupt-parent = <&mpic>;

			dfsrr;

		};



		serial0: serial@4500 {

			cell-index = <0>;

			device_type = "serial";

			compatible = "ns16550";

			reg = <0x4500 0x100>;

			clock-frequency = <0>;

			interrupts = <42 2>;

			interrupt-parent = <&mpic>;

		};



		serial1: serial@4600 {

			cell-index = <1>;

			device_type = "serial";

			compatible = "ns16550";

			reg = <0x4600 0x100>;

			clock-frequency = <0>;

			interrupts = <42 2>;

			interrupt-parent = <&mpic>;

		};



		spi@7000 {

			cell-index = <0>;

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "fsl,espi";

			reg = <0x7000 0x1000>;

			interrupts = <59 0x2>;

			interrupt-parent = <&mpic>;

			mode = "cpu";



			fsl_m25p80@0 {

				#address-cells = <1>;

				#size-cells = <1>;

				compatible = "fsl,espi-flash";

				reg = <0>;

				linux,modalias = "fsl_m25p80";

				modal = "s25sl128b";

				spi-max-frequency = <50000000>;

				mode = <0>;



				partition@0 {

					/* 512KB for u-boot Bootloader Image */

					reg = <0x0 0x00080000>;

					label = "SPI (RO) U-Boot Image";

					read-only;

				};



				partition@80000 {

					/* 512KB for DTB Image */

					reg = <0x00080000 0x00080000>;

					label = "SPI (RO) DTB Image";

					read-only;

				};



				partition@100000 {

					/* 4MB for Linux Kernel Image */

					reg = <0x00100000 0x00400000>;

					label = "SPI (RO) Linux Kernel Image";

					read-only;

				};



				partition@500000 {

					/* 4MB for Compressed RFS Image */

					reg = <0x00500000 0x00400000>;

					label = "SPI (RO) Compressed RFS Image";

					read-only;

				};



				partition@900000 {

					/* 7MB for JFFS2 based RFS */

					reg = <0x00900000 0x00700000>;

					label = "SPI (RW) JFFS2 RFS";

				};

			};

		};



		gpio: gpio-controller@f000 {

			#gpio-cells = <2>;

			compatible = "fsl,mpc8572-gpio";

			reg = <0xf000 0x100>;

			interrupts = <47 0x2>;

			interrupt-parent = <&mpic>;

			gpio-controller;

		};



		L2: l2-cache-controller@20000 {

			compatible = "fsl,p1020-l2-cache-controller";

			reg = <0x20000 0x1000>;

			cache-line-size = <32>;	// 32 bytes

			cache-size = <0x40000>; // L2,256K

			interrupt-parent = <&mpic>;

			interrupts = <16 2>;

		};



		dma@21300 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "fsl,eloplus-dma";

			reg = <0x21300 0x4>;

			ranges = <0x0 0x21100 0x200>;

			cell-index = <0>;

			dma-channel@0 {

				compatible = "fsl,eloplus-dma-channel";

				reg = <0x0 0x80>;

				cell-index = <0>;

				interrupt-parent = <&mpic>;

				interrupts = <20 2>;

			};

			dma-channel@80 {

				compatible = "fsl,eloplus-dma-channel";

				reg = <0x80 0x80>;

				cell-index = <1>;

				interrupt-parent = <&mpic>;

				interrupts = <21 2>;

			};

			dma-channel@100 {

				compatible = "fsl,eloplus-dma-channel";

				reg = <0x100 0x80>;

				cell-index = <2>;

				interrupt-parent = <&mpic>;

				interrupts = <22 2>;

			};

			dma-channel@180 {

				compatible = "fsl,eloplus-dma-channel";

				reg = <0x180 0x80>;

				cell-index = <3>;

				interrupt-parent = <&mpic>;

				interrupts = <23 2>;

			};

		};



		usb@22000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "fsl-usb2-dr";

			reg = <0x22000 0x1000>;

			interrupt-parent = <&mpic>;

			interrupts = <28 0x2>;

			phy_type = "ulpi";

		};



		usb@23000 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "fsl-usb2-dr";

			reg = <0x23000 0x1000>;

			interrupt-parent = <&mpic>;

			interrupts = <46 0x2>;

			phy_type = "ulpi";

		};



		sdhci@2e000 {

			compatible = "fsl,p1020-esdhc", "fsl,esdhc";

			reg = <0x2e000 0x1000>;

			interrupts = <72 0x2>;

			interrupt-parent = <&mpic>;

			/* Filled in by U-Boot */

			clock-frequency = <0>;

		};



		crypto@30000 {

			compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",

				     "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";

			reg = <0x30000 0x10000>;

			interrupts = <45 2 58 2>;

			interrupt-parent = <&mpic>;

			fsl,num-channels = <4>;

			fsl,channel-fifo-len = <24>;

			fsl,exec-units-mask = <0xbfe>;

			fsl,descriptor-types-mask = <0x3ab0ebf>;

		};



		mpic: pic@40000 {

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <2>;

			reg = <0x40000 0x40000>;

			compatible = "chrp,open-pic";

			device_type = "open-pic";

		};



		msi@41600 {

			compatible = "fsl,p1020-msi", "fsl,mpic-msi";

			reg = <0x41600 0x80>;

			msi-available-ranges = <0 0x100>;

			interrupts = <

				0xe0 0

				0xe1 0

				0xe2 0

				0xe3 0

				0xe4 0

				0xe5 0

				0xe6 0

				0xe7 0>;

			interrupt-parent = <&mpic>;

		};



		global-utilities@e0000 {	//global utilities block

			compatible = "fsl,p1020-guts";

			reg = <0xe0000 0x1000>;

			fsl,has-rstcr;

		};

	};



	pci0: pcie@ffe09000 {

		compatible = "fsl,mpc8548-pcie";

		device_type = "pci";

		#interrupt-cells = <1>;

		#size-cells = <2>;

		#address-cells = <3>;

		reg = <0 0xffe09000 0 0x1000>;

		bus-range = <0 255>;

		ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000

			  0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;

		clock-frequency = <33333333>;

		interrupt-parent = <&mpic>;

		interrupts = <16 2>;

		pcie@0 {

			reg = <0x0 0x0 0x0 0x0 0x0>;

			#size-cells = <2>;

			#address-cells = <3>;

			device_type = "pci";

			ranges = <0x2000000 0x0 0xa0000000

				  0x2000000 0x0 0xa0000000

				  0x0 0x20000000



				  0x1000000 0x0 0x0

				  0x1000000 0x0 0x0

				  0x0 0x100000>;

		};

	};



	pci1: pcie@ffe0a000 {

		compatible = "fsl,mpc8548-pcie";

		device_type = "pci";

		#interrupt-cells = <1>;

		#size-cells = <2>;

		#address-cells = <3>;

		reg = <0 0xffe0a000 0 0x1000>;

		bus-range = <0 255>;

		ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000

			  0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;

		clock-frequency = <33333333>;

		interrupt-parent = <&mpic>;

		interrupts = <16 2>;

		pcie@0 {

			reg = <0x0 0x0 0x0 0x0 0x0>;

			#size-cells = <2>;

			#address-cells = <3>;

			device_type = "pci";

			ranges = <0x2000000 0x0 0xc0000000

				  0x2000000 0x0 0xc0000000

				  0x0 0x20000000



				  0x1000000 0x0 0x0

				  0x1000000 0x0 0x0

				  0x0 0x100000>;

		};

	};

};

arch/powerpc/platforms/85xx/mpc85xx_rdb.c

+24 −0
Original line number Original line Diff line number Diff line
@@ -121,6 +121,7 @@ static int __init mpc85xxrdb_publish_devices(void) 
	return of_platform_bus_probe(NULL, mpc85xxrdb_ids, NULL);

	return of_platform_bus_probe(NULL, mpc85xxrdb_ids, NULL);

}

}

machine_device_initcall(p2020_rdb, mpc85xxrdb_publish_devices);

machine_device_initcall(p2020_rdb, mpc85xxrdb_publish_devices);

machine_device_initcall(p1020_rdb, mpc85xxrdb_publish_devices);





/*

/*

 * Called very early, device-tree isn't unflattened

 * Called very early, device-tree isn't unflattened
@@ -134,6 +135,15 @@ static int __init p2020_rdb_probe(void) 
	return 0;

	return 0;

}

}





static int __init p1020_rdb_probe(void)

{

	unsigned long root = of_get_flat_dt_root();



	if (of_flat_dt_is_compatible(root, "fsl,P1020RDB"))

		return 1;

	return 0;

}



define_machine(p2020_rdb) {

define_machine(p2020_rdb) {

	.name			= "P2020 RDB",

	.name			= "P2020 RDB",

	.probe			= p2020_rdb_probe,

	.probe			= p2020_rdb_probe,
@@ -147,3 +157,17 @@ define_machine(p2020_rdb) { 
	.calibrate_decr		= generic_calibrate_decr,

	.calibrate_decr		= generic_calibrate_decr,

	.progress		= udbg_progress,

	.progress		= udbg_progress,

};

};



define_machine(p1020_rdb) {

	.name			= "P1020 RDB",

	.probe			= p1020_rdb_probe,

	.setup_arch		= mpc85xx_rdb_setup_arch,

	.init_IRQ		= mpc85xx_rdb_pic_init,

#ifdef CONFIG_PCI

	.pcibios_fixup_bus	= fsl_pcibios_fixup_bus,

#endif

	.get_irq		= mpic_get_irq,

	.restart		= fsl_rstcr_restart,

	.calibrate_decr		= generic_calibrate_decr,

	.progress		= udbg_progress,

};