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Commit 5296cf2d authored by Daniel Mack's avatar Daniel Mack Committed by Mark Brown
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ASoC: McASP: set format parameters in dependence of the DAI format 



The FSDUR flag configures whether the frame clock uses a high phase of
only one bit or a full word. This has to be set depending on the DAI
format.

For other modes than DSP_B, the FSXDLY/FSRDLY fields have to be set to
1.

Signed-off-by: default avatarDaniel Mack <zonque@gmail.com>
Signed-off-by: default avatarMark Brown <broonie@opensource.wolfsonmicro.com>
parent 5b66aa2d

sound/soc/davinci/davinci-mcasp.c

+17 −4
Original line number Diff line number Diff line
@@ -477,6 +477,23 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, 
	struct davinci_audio_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);

	void __iomem *base = dev->base;



	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {

	case SND_SOC_DAIFMT_DSP_B:

	case SND_SOC_DAIFMT_AC97:

		mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);

		mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);

		break;

	default:

		/* configure a full-word SYNC pulse (LRCLK) */

		mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);

		mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);



		/* make 1st data bit occur one ACLK cycle after the frame sync */

		mcasp_set_bits(dev->base + DAVINCI_MCASP_TXFMT_REG, FSXDLY(1));

		mcasp_set_bits(dev->base + DAVINCI_MCASP_RXFMT_REG, FSRDLY(1));

		break;

	}



	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {

	case SND_SOC_DAIFMT_CBS_CFS:

		/* codec is clock and frame slave */
@@ -765,8 +782,6 @@ static void davinci_hw_param(struct davinci_audio_dev *dev, int stream) 
		else

			printk(KERN_ERR "playback tdm slot %d not supported\n",

				dev->tdm_slots);



		mcasp_clr_bits(dev->base + DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);

	} else {

		/* bit stream is MSB first with no delay */

		/* DSP_B mode */
@@ -779,8 +794,6 @@ static void davinci_hw_param(struct davinci_audio_dev *dev, int stream) 
		else

			printk(KERN_ERR "capture tdm slot %d not supported\n",

				dev->tdm_slots);



		mcasp_clr_bits(dev->base + DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);

	}

}