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Commit 51ce4db1 authored by Rodrigo Vivi's avatar Rodrigo Vivi Committed by Daniel Vetter
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drm/i915/bdw: WaProgramL3SqcReg1Default 



Program the default initial value of the L3SqcReg1 on BDW for performance

v2: Default confirmed and using intel_ring_emit_wa as Mika pointed out.

v3: Spec shows now a different value. It tells us to set to 0x784000
    instead the 0x610000 that is there already.
    Also rebased after a long time so using WA_WRITE now.

Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 474d1ec4

drivers/gpu/drm/i915/i915_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -5336,6 +5336,9 @@ enum skl_disp_power_wells { 
#define GEN7_L3SQCREG1				0xB010

#define  VLV_B0_WA_L3SQCREG1_VALUE		0x00D30000



#define GEN8_L3SQCREG1				0xB100

#define  BDW_WA_L3SQCREG1_DEFAULT		0x784000



#define GEN7_L3CNTLREG1				0xB01C

#define  GEN7_WA_FOR_GEN7_L3_CONTROL			0x3C47FF8C

#define  GEN7_L3AGDIS				(1<<19)

drivers/gpu/drm/i915/intel_ringbuffer.c

+3 −0
Original line number Diff line number Diff line
@@ -853,6 +853,9 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring) 
			    GEN6_WIZ_HASHING_MASK,

			    GEN6_WIZ_HASHING_16x4);



	/* WaProgramL3SqcReg1Default:bdw */

	WA_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);



	return 0;

}